/**
 @file sys_at_mac.c

 @author  Copyright (C) 2021 Centec Networks Inc.  All rights reserved.

 @date 2021-03-10

 @version v2.0

*/

/// TEMP COMMENT
/// mac.c content :
///  #1, mac pcs fec config/reset
///  #2, port API
///  #3, dynamic switch
/****************************************************************************
 *
* Header Files
*
****************************************************************************/
#include "sys_usw_chip.h"
#include "sys_usw_dmps.h"
#include "sys_usw_datapath.h"
#include "sal.h"
#include "ctc_port.h"
#include "ctc_error.h"
#include "ctc_debug.h"
#include "ctc_interrupt.h"
#include "ctc_warmboot.h"
#include "drv_api.h"
#include "usw/include/drv_common.h"
#include "sys_at_datapath.h"
#include "sys_usw_dmps_db.h"
#include "sys_at_mac.h"
#include "sys_usw_common.h"
#include "sys_usw_datapath.h"

#include "sys_usw_peri.h"
#include "sys_usw_stats_api.h"
#include "sys_usw_dmps.h"
#include "sys_usw_interrupt.h"
#include "sys_usw_port.h"
#include "sys_usw_mac.h"
#include "sys_usw_wb_common.h"
#include "sys_usw_mcu.h"
#include "sys_usw_register.h"

#include "drv_api.h"
#include "usw/include/drv_common.h"
#include "sys_usw_register.h"
#include "sys_at_serdes.h"
#include "sys_usw_dmps_mc_reg.h"
#include "sys_usw_dmps_shared_reg.h"
#include "sys_usw_dmps_reg.h"
#include "sys_usw_phy.h"

extern sal_file_t g_tm_dump_fp;
extern uint8 g_dmps_dbg_sw;

uint8 g_at_hata_en = TRUE; /*default enable HATA*/

uint8 g_print_cpumac = 0;

extern uint8 g_print_tbl;
extern uint32 g_port_link_mode;

extern int32 
_sys_at_serdes_speed_switch_proc(uint8 lchip, uint16 serdes_id, uint8 serdes_speed);
extern int32
_sys_at_serdes_check_and_recover_pll_ready(uint8 lchip, uint16 serdes_id, uint8 serdes_speed);

extern int32
_sys_at_datapath_get_port_chan_by_serdes(uint8 lchip, uint16 logic_serdes, uint16* p_chan, uint16* p_dport);
extern int32
_sys_at_datapath_get_serdes_chan_by_lport(uint8 lchip, uint16 dport, uint16* p_chan, uint16* p_logic_serdes);
extern int32
_sys_at_datapath_delete_relation(uint8 lchip, uint16 logical_serdes);
extern int32
sys_usw_add_port_to_channel(uint8 lchip, uint16 lport, uint16 channel, uint8 is_pp);
extern int32
_sys_at_datapath_get_free_chan(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id,
                                uint8 free_num, uint16* free_chan, uint16* free_sub_chan, uint16* free_mac_client, uint8 dir_bmp);
extern int32
_sys_at_datapath_check(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id, sys_dmps_change_chan_info_t* info, uint8 dir, uint8 check_bw);
extern int32
_sys_at_datapath_xpipe_resource_alloc(uint8 lchip, uint16 dport, uint8 chan_num, uint16* chan_list, uint8 dir_bmp);
extern int32
_sys_at_datapath_set_qmgr_deq_scan_bmp(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 pp_chan, uint32 value);

extern int32
sys_usw_phy_set_phy_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, void* p_value);
extern int32
sys_usw_phy_get_phy_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, void* p_value);
extern int32
sys_at_datapath_set_priority(uint8 lchip, uint16 dport, uint32 value);
extern uint32
_sys_at_datapath_get_serdes_support_speed_bmp(uint8 lchip, uint8 chip_type, uint16 logic_serdes);
extern int32
_sys_at_datapath_resource_alloc_chan(uint8 lchip, uint16 chan_id, uint8 enable, uint8 dir_bmp, uint8 cfg_nettx_credit);
extern int32 
_sys_at_datapath_common_calendar(int16 entry_num, uint32 count, uint32 *p_speed, uint8 *p_error, uint16 *p_walk_end, uint16 *p_cal);

int32
_sys_at_mac_set_mac_rx_en(uint8 lchip, uint16 dport, uint32 enable);
int32
_sys_at_mac_get_cl37_auto_neg(uint8 lchip, uint16 dport, uint32 type, uint32* p_value);
int32
_sys_at_mac_set_link_intr(uint8 lchip, uint16 dport, uint8 enable);
int32
_sys_at_mac_get_link_intr(uint8 lchip, uint16 mac_id, uint32* enable);
int32
_sys_at_mac_set_pcs_rst(uint8 lchip, uint16 dport, uint8 dir, uint8 reset);
int32
_sys_at_mac_wait_rx_buf_empty(uint8 lchip, uint16 mac_id);
int32
_sys_at_mac_get_unidir_en(uint8 lchip, uint16 dport, uint32* p_value);
int32
_sys_at_mac_set_mac_pkt_en(uint8 lchip, uint16 dport, uint8 dir, uint32 enable);
int32
_sys_at_mac_disable_queue_drop(uint8 lchip, uint16 dport);
int32
_sys_at_mac_set_mcmac_tx_cal(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 entry_id, uint8 value);
int32
_sys_at_mac_set_mcmac_rx_cal(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 entry_id, uint8 value);
int32
_sys_at_mac_pcs_pre_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id);
int32
_sys_at_mac_init_cl73_ability(uint8 lchip, uint8 core_id, uint16 psd);
extern int32
_sys_at_serdes_get_loopback(uint8 lchip, void* p_data);
extern int32
_sys_at_datapath_dynamic_switch_check(uint8 lchip, sys_dmps_ds_list_t* target);
extern int32
_sys_at_cpumac_get_link_up(uint8 lchip, uint16 dport, uint32* p_is_up, uint32 is_phy_link, uint8 mii_link_type);
extern int32
_sys_at_mac_get_mii_link_status(uint8 lchip, uint16 mac_id, uint8 mii_link_type, uint32* p_value);
extern void
_sys_usw_port_api_dmps_msg_sem_give(uint8 lchip);
int32
_sys_at_mac_get_fec(uint8 lchip, uint16 dport, uint32* p_value);
extern int32
sys_at_serdes_psd_to_serdes(uint8 lchip, uint16 psd, uint16* serdes_id);
extern void 
_sys_usw_mac_show_cl73_ability(uint32 value);
extern uint8 
_sys_at_datapath_get_serdes_type(uint16 logic_serdes_dc);
extern int32
sys_at_mcu_get_anlt_state(uint8 lchip, uint16 dport, uint32* p_state);
extern int32
sys_at_mcu_send_link_up_intr(uint8 lchip, uint16 dport);
extern int32
sys_at_mcu_send_link_adjust_intr(uint8 lchip, uint16 dport);
//#define SYS_DMPS_DUMP_PRINT  if(g_dmps_dbg_sw && g_tm_dump_fp) sal_fprintf

#ifdef DRV_IOW_FIELD
#undef DRV_IOW_FIELD
#define DRV_IOW_FIELD(lchip, memid, inst_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write %-35s 0 inst %-5d field: %-45s 0x%x\n", \
                TABLE_NAME(lchip, memid), inst_id, fld_str, *value); \
        }\
    }\
    while(0)

#endif

/* DRV_IOW_FIELD extender, for index Not Zero */
#define DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, memid, inst_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            if ((255 != pp_id) && (255 != dp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u pp %u dp %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id, pp_id, dp_id); \
            }\
            else if ((255 != pp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u pp %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id, pp_id); \
            }\
            else\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id); \
            }\
        }\
    }\
    while(0)

#define DRV_IOW_ENTRY(lchip, memid, inst_id, entry_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d\n", \
                TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id); \
        }\
    }\
    while(0)

#define DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, memid, inst_id, entry_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            if ((255 != pp_id) && (255 != dp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u pp %u dp %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id, pp_id, dp_id); \
            }\
            else if ((255 != pp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u pp %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id, pp_id); \
            }\
            else\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id); \
            }\
        }\
    }\
    while(0)

#define DP_DEBUG_FUNCTION_CALLED_PRINT() \
    do \
    { \
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw)) \
        {\
            sal_fprintf(g_tm_dump_fp, "------ %s enter ----------------\n", __func__); \
        }\
    } \
    while(0)

#define DP_DEBUG_FUNCTION_RETURN_PRINT() \
    do \
    { \
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw)) \
        {\
            sal_fprintf(g_tm_dump_fp, "------ %s return ----------------\n", __func__); \
        }\
    } \
    while(0)

#define SYS_AT_MAC_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))

extern int32
_sys_at_datapath_dynamic_switch(uint8 lchip, sys_dmps_ds_list_t* target, uint8 is_switch_serdes);


/************************* Mac&Pcs public info *************************/
uint32 g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {128        , 128         , 128         , 128         , 128          , 128          , 128           , 128          , 128        , 128        ,
     128        , 128         , 128         , 128         , 192          , 192          , 192           , 192          , 192        ,
     192        , 192         , 192         , 192         , 192          , 192          , 192           , 192          ,
     192        , 192         , 256         , 256         , 256          , 256          , 512           , 512          , 128}, /* McMacMiiTx_cfgMcMacMiiTxBuffThrd */
    {5          , 5           , 6           , 6           , 6            , 7            , 7             , 8            , 8          , 8          ,
     8          , 8           , 8           , 8           , 9            , 9            , 9             , 9            , 9          ,
     9          , 9           , 9           , 9           , 9            , 9            , 10            , 10           ,
     10         , 10          , 11          , 11          , 11           , 11           , 12            , 12           , 0}, /* McMacMiiTx_cfgMcMacTxChanSpeed */
    {3          , 3           , 4           , 4           , 4            , 3            , 3             , 4            , 4          , 4          ,
     5          , 5           , 5           , 5           , 4            , 4            , 4             , 5            , 5          ,
     5          , 5           , 6           , 6           , 7            , 7            , 5             , 5            ,
     6          , 6           , 5           , 5           , 6            , 6            , 6             , 6            , 0}, /* McMacMiiTx_cfgMcMacTxLaneSpeed */
    {0          , 0           , 0           , 0           , 1            , 0            , 0             , 0            , 1          , 1          ,
     0          , 1           , 1           , 1           , 0            , 1            , 1             , 0            , 1          ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 0}, /* McMacMiiTx_cfgMcMacTxRsFecEn */
    {0          , 0           , 0           , 0           , 2            , 0            , 0             , 0            , 2          , 1          ,
     0          , 2           , 1           , 3           , 0            , 2            , 1             , 0            , 2          ,
     1          , 3           , 1           , 3           , 1            , 3            , 1             , 3            ,
     1          , 3           , 1           , 3           , 1            , 3            , 1             , 3            , 0}, /* McMacMiiTx_cfgMcMacTxRsFecMode */
    {0          , 0           , 0           , 0           , 1            , 1            , 1             , 1            , 1          , 1          ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 1          ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 0}, /* McMacMiiTx_cfgMcMacTxAmInsertEn */
    {0          , 0           , 0           , 0           , 5119         , 4095         , 4095          , 4095         , 5119       , 5119       ,
     4095       , 5119        , 5119        , 5119        , 20479        , 20479        , 20479         , 20479        , 20479      ,
     20479      , 20479       , 20479       , 20479       , 20479        , 20479        , 20479         , 20479        ,
     20479      , 20479       , 40959       , 40959       , 40959        , 40959        , 81919         , 81919        , 0}, /* McMacMiiTx_cfgMcMacTxAmInterval */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            ,
     0          , 0           , 1           , 1           , 0            , 0            , 0             , 0            , 0}, /* McMacMiiTx_cfgMcMacMiiTxRdMask */
    {96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           , 96         , 96         ,
     96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           , 96         ,
     96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           ,
     96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           , 96}, /* McMacMiiTx_cfgMcMacMiiTxBuffLowThrd */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0}, /* McMacMiiTx_cfgMcMacTxOverClockEn */
};

uint8 g_mac_mii_rx_cfg_by_fec_speed[McMacMiiRx_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {28         , 28          , 28          , 28          , 28           , 28           , 28            , 28           , 28         , 28         ,
     28         , 28          , 28          , 28          , 28           , 28           , 28            , 28           , 28         ,
     28         , 28          , 28          , 28          , 28           , 28           , 60            , 60           ,
     60         , 60          , 124         , 124         , 124          , 124          , 252           , 252          , 28}, /* McMacMiiRx_cfgMcMacMiiRxBuffMaxDepth */
};

uint8 g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     1          , 1           , 1           , 1           , 0            , 0            , 0             , 1            , 1          ,
     1          , 1           , 2           , 2           , 2            , 2            , 1             , 1            ,
     2          , 2           , 1           , 1           , 2            , 2            , 2             , 2            , 0}, /* McPcs800PhyLane_cfgPmaWidth */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 1           , 1           , 1            , 1            , 0             , 0            ,
     1          , 1           , 0           , 0           , 1            , 1            , 1             , 1            , 0}, /* McPcs800PhyLane_cfgLaneBitDemuxEn */
    {0          , 1           , 0           , 1           , 0            , 0            , 1             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0}, /* McPcs800PhyLane_cfgFcFecEn */
    {0          , 0           , 0           , 0           , 1            , 0            , 0             , 0            , 1          , 1          ,
     0          , 1           , 1           , 1           , 0            , 1            , 1             , 0            , 1          ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 0}, /* McPcs800PhyLane_cfgRsFecEn */
    {8          , 8           , 8           , 8           , 8            , 8            , 8             , 8            , 8          , 8          ,
     8          , 8           , 8           , 8           , 8            , 8            , 8             , 8            , 8          ,
     8          , 8           , 8           , 8           , 8            , 8            , 8             , 8            ,
     8          , 8           , 8           , 8           , 8            , 8            , 8             , 8            , 8}, /* McPcs800PhyLane_cfgTxLaneAsyncFifoAFullThrd */
    {2          , 2           , 2           , 2           , 2            , 2            , 2             , 2            , 2          , 2          ,
     2          , 2           , 2           , 2           , 2            , 2            , 2             , 2            , 2          ,
     2          , 2           , 2           , 2           , 2            , 2            , 2             , 2            ,
     2          , 2           , 2           , 2           , 2            , 2            , 2             , 2            , 2}, /* McPcs800PhyLane_cfgTxLaneAsyncFifoStartThrd */
    {2          , 2           , 2           , 2           , 2            , 2            , 2             , 2            , 2          , 2          ,
     2          , 2           , 2           , 2           , 2            , 2            , 2             , 2            , 2          ,
     2          , 2           , 2           , 2           , 16           , 16           , 2             , 2            ,
     16         , 16          , 2           , 2           , 2            , 2            , 2             , 2            , 2}, /* McPcs800PhyLane_cfgTxBufStartRdThrd */
    {4          , 4           , 6           , 6           , 5            , 4            , 4             , 6            , 5          , 5          ,
     10         , 8           , 8           , 8           , 6            , 5            , 5             , 10           , 8          ,
     8          , 8           , 15          , 15          , 15           , 15           , 8             , 8            ,
     15         , 15          , 8           , 8           , 15           , 15           , 15            , 15           , 4}, /* McPcs800PhyLane_cfgTxAsyncFifoCreditThrd */
};

uint32 g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
    {5          , 5           , 6           , 6           , 6            , 7            , 7             , 8            , 8          , 8          ,
     8          , 8           , 8           , 8           , 9            , 9            , 9             , 9            , 9          ,
     9          , 9           , 9           , 9           , 9            , 9            , 10            , 10           ,
     10         , 10          , 11          , 11          , 11           , 11           , 12            , 12           , 0}, /* McPcs400RxLane_cfgRxChanSpeed */
    {3          , 3           , 4           , 4           , 4            , 3            , 3             , 4            , 4          , 4          ,
     5          , 5           , 5           , 5           , 4            , 4            , 4             , 5            , 5          ,
     5          , 5           , 6           , 6           , 7            , 7            , 5             , 5            ,
     6          , 6           , 5           , 5           , 6            , 6            , 6             , 6            , 0}, /* McPcs400RxLane_cfgRxLaneSpeed */
    {16383      , 16383       , 16383       , 16383       , 67583        , 16382        , 16382         , 16382        , 33791      , 34815      ,
     16382      , 33791       , 34815       , 34815       , 16382        , 67583        , 69631         , 16382        , 67583      ,
     69631      , 69631       , 69631       , 69631       , 69631        , 69631        , 34815         , 34815        ,
     34815      , 34815       , 34815       , 34815       , 34815        , 34815        , 34815         , 34815        , 0}, /* McPcs400RxLane_cfgRxAmInterval */
    {0          , 0           , 0           , 0           , 1            , 0            , 0             , 0            , 1          , 1          ,
     0          , 1           , 1           , 1           , 0            , 1            , 1             , 0            , 1          ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 0}, /* McPcs400RxLane_cfgRxRsFecEn */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 1             , 1            ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 0}, /* McPcs400RxLane_cfgRxCwmLockFsmMode */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 0           , 0           , 1            , 1            , 0             , 0            ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0}, /* McPcs400RxLane_cfgRxCl161Mode */
};

uint8 g_pcs_400_rx_chan_cfg_by_fec_speed[McPcs400Rx_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
    {0          , 0           , 0           , 0           , 2            , 0            , 0             , 0            , 2          , 1          ,
     0          , 2           , 1           , 3           , 0            , 2            , 1             , 0            , 2          ,
     1          , 3           , 1           , 3           , 1            , 3            , 1             , 3            ,
     1          , 3           , 1           , 3           , 1            , 3            , 1             , 3            , 0}, /* McPcs400Rx_cfgRxFecMode */
    {159        , 159         , 159         , 159         , 159          , 159          , 159           , 79           , 79         , 79         ,
     39         , 79          , 79          , 79          , 31           , 79           , 79            , 15           , 79         ,
     79         , 79          , 79          , 79          , 79           , 79           , 79            , 79           ,
     79         , 79          , 79          , 79          , 79           , 79           , 79            , 79           , 159}, /* McPcs400Rx_cfgRxDskMaxAddr */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 1             , 1            ,
     1          , 1           , 1           , 1           , 1            , 1            , 1             , 1            , 0}, /* McPcs400Rx_cfgRxFecCwmSfBitsEn */
};

uint8 g_mac_credit_ctl_by_fec_speed[McMacCreditCtl_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
    {12         , 12          , 12          , 12          , 16           , 16           , 16            , 16           , 20         , 20         ,
     16         , 20          , 20          , 20          , 20           , 24           , 24            , 20           , 24         ,
     24         , 24          , 24          , 24          , 28           , 28           , 36            , 36           ,
     40         , 40          , 52          , 52          , 52           , 52           , 92            , 92           , 12}, /* McMacCreditCtl_cfgTxCreditThrd */
};

uint8 g_mac_rx_ctl_by_fec_speed[McMacMacRx_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
    {5          , 5           , 6           , 6           , 6            , 7            , 7             , 8            , 8          , 8          ,
     8          , 8           , 8           , 8           , 9            , 9            , 9             , 9            , 9          ,
     9          , 9           , 9           , 9           , 9            , 9            , 10            , 10           ,
     10         , 10          , 11          , 11          , 11           , 11           , 12            , 12           , 0}, /* McMacMacRx_cfgMcMacRxSpeed */
};

uint8 g_hata_rx_cfg_by_fec_speed[McHataRsCfg_TOTAL_CNT][AT_MAX_MODE_FEC] =
{
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
    {0          , 0           , 0           , 0           , 2            , 0            , 0             , 0            , 2          , 1          ,
     0          , 2           , 1           , 3           , 0            , 2            , 1             , 0            , 2          ,
     1          , 3           , 1           , 3           , 1            , 3            , 1             , 3            ,
     1          , 3           , 1           , 3           , 1            , 3            , 1             , 3            , 0}, /* McHataRsCfg_Mode */
};

int32
_sys_at_mac_get_cal_by_speed(uint8 lchip, uint8 idx, uint8 if_mode, uint8* cal_value, uint8* step)
{
    uint8  entry_num = 0;
    uint8  cnt       = 0;
    uint8  unit      = 1;
    uint16 core_pll  = 0;
    uint32 value     = 0;

    SYS_AT_IF_MODE_TO_SPEED_VALUE(if_mode, value);

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
    if (1350 == core_pll)
    {
        /* 1350M: calculate by unit of 50G */
        value = ((value < 50) && (value > 0)) ? 50 : value;
        unit  = 50;
    }
    else if (900 == core_pll)
    {
        /* 900: calculate by unit of 25G */
        value = ((value < 25) && (value > 0)) ? 25 : ((40 == value) ? 50 : value);
        unit  = 25;
    }

    entry_num  = value / unit;
    for (cnt = 1; cnt < entry_num; cnt++)
    {
        cal_value[idx + cnt] = cal_value[idx];
    }

    *step = (0 == entry_num) ? 1 : entry_num;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cal_by_lane(uint8 lchip, uint8 idx, uint8 if_mode, uint8* cal_value)
{
    uint8 lane_num = 0;
    uint8 cnt      = 0;

    SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, lane_num);

    for (cnt = 1; cnt < lane_num; cnt++)
    {
        cal_value[idx + cnt] = cal_value[idx];
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_stats_init_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 value  = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;
    McMacStatsInit_m mcmac_stats_init;

    index  = DRV_INS(mac_group_id, 0);
    tbl_id = McMacStatsInit_t;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_init));

    /* cfg quadSgmac0Init */
    value  = 1;
    fld_id = McMacStatsInit_quadSgmac0Init_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &value, &mcmac_stats_init);

    /* cfg quadSgmac1Init */
    value  = 1;
    fld_id = McMacStatsInit_quadSgmac1Init_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &value, &mcmac_stats_init);
    
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_init));
    
    return CTC_E_NONE;
}


int32
_sys_at_mac_set_mcmac_init_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 value  = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;
    McMacInit_m mcmac_init;

    index  = DRV_INS(mac_group_id, 0);
    tbl_id = McMacInit_t;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_init));

    value  = 1;
    fld_id = McMacInit_init_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &value, &mcmac_init);
    
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_init));
    
    return CTC_E_NONE;
}

int32
_sys_at_mac_set_hss_lane_cfg_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id,
                                    uint8 pcs_half_idx, uint8 idx,
                                    sys_at_hss_lane_cfg_list_item_t cfg_type, uint8 cfg_value)
{
    uint16 step   = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 value  = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;

    HssLaneCfg_m hss_lane_cfg;

    index  = DRV_INS(2 * mac_group_id + pcs_half_idx, 0);
    tbl_id = HssLaneCfg_t;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &hss_lane_cfg));
    value  = cfg_value;

    switch (cfg_type)
    {
        case HssLaneCfg_cfgAnethTxReadyLane:
            step   = HssLaneCfg_cfgAnethTxReadyLane1_f - HssLaneCfg_cfgAnethTxReadyLane0_f;
            fld_id = HssLaneCfg_cfgAnethTxReadyLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgForcePmaReady4AnethEnLane:
            step   = HssLaneCfg_cfgForcePmaReady4AnethEnLane1_f - HssLaneCfg_cfgForcePmaReady4AnethEnLane0_f;
            fld_id = HssLaneCfg_cfgForcePmaReady4AnethEnLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgForcePmaReady4AnethValueLane:
            step   = HssLaneCfg_cfgForcePmaReady4AnethValueLane1_f - HssLaneCfg_cfgForcePmaReady4AnethValueLane0_f;
            fld_id = HssLaneCfg_cfgForcePmaReady4AnethValueLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgForcePmaReady4PcsEnLane:
            step   = HssLaneCfg_cfgForcePmaReady4PcsEnLane1_f - HssLaneCfg_cfgForcePmaReady4PcsEnLane0_f;
            fld_id = HssLaneCfg_cfgForcePmaReady4PcsEnLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgForcePmaReady4PcsValueLane:
            step   = HssLaneCfg_cfgForcePmaReady4PcsValueLane1_f - HssLaneCfg_cfgForcePmaReady4PcsValueLane0_f;
            fld_id = HssLaneCfg_cfgForcePmaReady4PcsValueLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgForcePmaReady4SyncEEnLane:
            step   = HssLaneCfg_cfgForcePmaReady4SyncEEnLane1_f - HssLaneCfg_cfgForcePmaReady4SyncEEnLane0_f;
            fld_id = HssLaneCfg_cfgForcePmaReady4SyncEEnLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgForcePmaReady4SyncEValueLane:
            step   = HssLaneCfg_cfgForcePmaReady4SyncEValueLane1_f - HssLaneCfg_cfgForcePmaReady4SyncEValueLane0_f;
            fld_id = HssLaneCfg_cfgForcePmaReady4SyncEValueLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgHssTxOutSelLane:
            step   = HssLaneCfg_cfgHssTxOutSelLane1_f - HssLaneCfg_cfgHssTxOutSelLane0_f;
            fld_id = HssLaneCfg_cfgHssTxOutSelLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgPmaReady4AnethMaskLane:
            step   = HssLaneCfg_cfgPmaReady4AnethMaskLane1_f - HssLaneCfg_cfgPmaReady4AnethMaskLane0_f;
            fld_id = HssLaneCfg_cfgPmaReady4AnethMaskLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgPmaReady4PcsMaskLane:
            step   = HssLaneCfg_cfgPmaReady4PcsMaskLane1_f - HssLaneCfg_cfgPmaReady4PcsMaskLane0_f;
            fld_id = HssLaneCfg_cfgPmaReady4PcsMaskLane0_f + step * idx;
            break;
        case HssLaneCfg_cfgPmaReady4SyncEMaskLane:
            step   = HssLaneCfg_cfgPmaReady4SyncEMaskLane1_f - HssLaneCfg_cfgPmaReady4SyncEMaskLane0_f;
            fld_id = HssLaneCfg_cfgPmaReady4SyncEMaskLane0_f + step * idx;
            break;
        default:
            return CTC_E_NONE;
    }
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 2 * mac_group_id + pcs_half_idx, fld_id, &value, &hss_lane_cfg);

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &hss_lane_cfg));

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_mcmac_cal_ctrl_1to2_macagg(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[4] = {{0}};

    sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgTxWalkerEnd_f,  15);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgRxWalkerEnd_f,  15);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_cal_ctrl(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_mcmac_cal_ctrl(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  fld_num = 0;
    uint8  index   = 0;
    reg_field_info_t fld_info[4] = {{0}};

    if (SYS_AT_IS_1TO2_GROUP(lchip, mac_group_id))
    {
        sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgTxWalkerEnd_f,  15);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgRxWalkerEnd_f,  7);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgMcMacTxReady_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgMcMacRxReady_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_cal_ctrl(lchip, core_id, mac_group_id, fld_num, fld_info));

        for (index = 0; index < 4; index++)
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal(lchip, core_id, mac_group_id, 4 * index + 2, 3));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal(lchip, core_id, mac_group_id, 4 * index + 3, 7));
        }
#if 0
        fld_num = 0;
        sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
        SET_REG_FIELD_INFO(fld_info, fld_num, 7, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacMiiTxRdMask_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
#endif
    }
    else
    {
        sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgTxWalkerEnd_f,  7);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgRxWalkerEnd_f,  7);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgMcMacTxReady_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgMcMacRxReady_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_cal_ctrl(lchip, core_id, mac_group_id, fld_num, fld_info));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_rx_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 mac_idx,
                                uint8 if_mode, uint8 fec_type)
{
    uint8  fld_num = 0;
    uint8  mode    = 0;
    reg_field_info_t fld_info[2] = {{0}};

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f, 1);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxSpeed_f,
                        g_mac_rx_ctl_by_fec_speed[McMacMacRx_cfgMcMacRxSpeed][mode]);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_tx_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 mac_idx,
                                uint8 if_mode, uint8 fec_type)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[3] = {{0}};

    sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f,   0);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacPmInterval_f, 4095);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_mii_tx_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 mac_idx,
                                    uint8 if_mode, uint8 fec_type, uint8 ocs)
{
    uint32 cfg_value = 0;
    uint16 core_pll  = 0;
    uint8  mode      = DMPS_MAX_MODE_FEC;
    uint8  fld_num   = 0;
    reg_field_info_t fld_info[12] = {{0}};
    uint32 fre900_mac_mii_tx_buff_thrd[AT_MAX_MODE_FEC] =
    {
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
     128        , 128         , 128         , 128         , 128          , 128          , 128           , 128          , 128        , 128        ,
     128        , 128         , 128         , 128         , 192          , 192          , 192           , 192          , 192        ,
     192        , 192         , 192         , 192         , 192          , 192          , 256           , 256          ,
     256        , 256         , 320         , 320         , 320          , 320          , 320           , 320          , 0}; /* McMacMiiTx_cfgMcMacMiiTxBuffThrd */
    uint32 ocs_mac_mii_tx_buff_thrd[AT_MAX_MODE_FEC] =
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {128        , 128         , 128         , 128         , 128          , 128          , 128           , 128          , 128        , 128        ,
     128        , 128         , 128         , 128         , 192          , 256          , 256           , 256          , 256        ,
     256        , 256         , 256         , 256         , 256          , 256          , 256           , 256          ,
     256        , 256         , 512         , 512         , 512          , 512          , 512           , 512          , 128};
    uint32 ocs_mac_mii_tx_buff_low_thrd[AT_MAX_MODE_FEC] =
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           , 96         , 96         ,
     96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           , 96         ,
     96         , 96          , 96          , 96          , 96           , 96           , 96            , 96           ,
     96         , 96          , 256         , 256         , 256          , 256          , 256           , 256          , 96 };
    uint32 ocs_mac_tx_over_clock_en[AT_MAX_MODE_FEC] =
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          , 0          ,
     0          , 0           , 0           , 0           , 0            , 0            , 0             , 0            , 0          ,
     0          , 0           , 1           , 1           , 1            , 1            , 0             , 0            ,
     1          , 1           , 0           , 0           , 1            , 1            , 1             , 1            , 0 };

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));
    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);

    sal_memset(fld_info, 0xff, 12 * sizeof(reg_field_info_t));

    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxChanSpeed_f,
                        g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxChanSpeed][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxLaneSpeed_f,
                        g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxLaneSpeed][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecEn_f,
                        g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxRsFecEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecMode_f,
                        g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxRsFecMode][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInsertEn_f,
                        g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxAmInsertEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInterval_f,
                        g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxAmInterval][mode]);
    if (SYS_AT_IS_1TO2_MAC_AGG_GROUP(lchip, mac_group_id) && (1350 == core_pll))
    {
         SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacMiiTxRdMask_f, 0);
    }
    else
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacMiiTxRdMask_f,
                            g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacMiiTxRdMask][mode]);
    }

    if (900 == core_pll)
    {
        cfg_value = fre900_mac_mii_tx_buff_thrd[mode];
    }
    else if (CTC_CHIP_SERDES_OCS_MODE_NONE != ocs)
    {
        cfg_value = ocs_mac_mii_tx_buff_thrd[mode];
    }
    else
    {
        cfg_value = g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacMiiTxBuffThrd][mode];
    }
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacMiiTxBuffThrd_f, cfg_value);

    if (CTC_CHIP_SERDES_OCS_MODE_NONE != ocs)
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacMiiTxBuffLowThrd_f,
                            ocs_mac_mii_tx_buff_low_thrd[mode]);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxOverClockEn_f,
                            ocs_mac_tx_over_clock_en[mode]);
    }
    else
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacMiiTxBuffLowThrd_f,
                            g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacMiiTxBuffLowThrd][mode]);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxOverClockEn_f,
                            g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxOverClockEn][mode]);
    }

#ifdef EMULATION_ENV
    uint8  chip_type = SYS_AT_GET_CHIP_TYPE(lchip);

    if (SYS_AT_IS_1PP(chip_type))
    {
        if ((18 == mac_group_id) || (19 == mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, CTC_CHIP_SERDES_NONE_MODE, SYS_AT_MAC_FEC_TYPE_NONE, &mode));
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecEn_f,
                                g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxRsFecEn][mode]);
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInsertEn_f,
                                g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxAmInsertEn][mode]);
        }
    }
    else
    {
#ifndef PCS_ONLY
#ifndef EMULATOR_ENV
    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, CTC_CHIP_SERDES_NONE_MODE, SYS_AT_MAC_FEC_TYPE_NONE, &mode));
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecEn_f,
                            g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxRsFecEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInsertEn_f,
                            g_mac_mii_tx_cfg_by_fec_speed[McMacMiiTx_cfgMcMacTxAmInsertEn][mode]);
#endif
#endif
    }
#endif

    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_pause_tx_ctl(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 mac_idx,
                                    uint8 if_mode, uint8 fec_type)
{
    uint8  fld_num    = 0;
    uint32 value      = 0;
    uint32 speed_mode = 0;
    reg_field_info_t fld_info[1] = {{0}};

    SYS_DMPS_GET_PORT_SPEED(if_mode, speed_mode);
    SYS_AT_SPEED_MODE_TO_PAUSE_TIMER_DEC_VALUE(speed_mode, value);

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacPauseTxCtl_mcMacPauseTxCfg_0_cfgMcMacTxPauseTimerDecValue_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_pause_tx_ctl(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_tx_cal(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 entry_id, uint8 value)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacTxCal_calEntry_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_cal(lchip, core_id, mac_group_id, entry_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_rx_cal(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 entry_id, uint8 value)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacRxCal_calEntry_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_cal(lchip, core_id, mac_group_id, entry_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_tx_chan_lane_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 physic_lane_id, uint8 logic_lane_id)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, physic_lane_id, McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f, logic_lane_id);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_chan_id_lane_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_credit_ctl_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 mac_idx,
                                    uint8 if_mode, uint8 fec_type, uint8 ocs)
{
    uint32 cfg_value = 0;
    uint16 core_pll  = 0;
    uint8  mode      = DMPS_MAX_MODE_FEC;
    uint8  fld_num   = 0;
    reg_field_info_t fld_info[1] = {{0}};
    uint8  ocs_mac_tx_credit_thrd[AT_MAX_MODE_FEC] =
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {12         , 12          , 12          , 12          , 16           , 16           , 16            , 16           , 20         , 20         ,
     16         , 20          , 20          , 20          , 24           , 28           , 28            , 24           , 28         ,
     28         , 28          , 24          , 24          , 28           , 28           , 36            , 36           ,
     44         , 44          , 56          , 56          , 56           , 56           , 96            , 96           , 12};
    uint8  fre900_mac_credit_ctl_thrd[AT_MAX_MODE_FEC] = 
    {
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
     12         , 12          , 16          , 16          , 16           , 16           , 16            , 20           , 24         , 20         ,
     20         , 24          , 20          , 24          , 28           , 32           , 32            , 28           , 32         ,
     32         , 32          , 32          , 32          , 32           , 36           , 48            , 48           ,
     52         , 56          , 72          , 72          , 72           , 72           , 132           , 132          , 0}; /* McMacCreditCtl_cfgTxCreditThrd */
    
    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
    if (900 == core_pll)
    {
        cfg_value = fre900_mac_credit_ctl_thrd[mode];
    }
    else if (CTC_CHIP_SERDES_OCS_MODE_NONE != ocs)
    {
        cfg_value = ocs_mac_tx_credit_thrd[mode];
    }
    else
    {
        cfg_value = g_mac_credit_ctl_by_fec_speed[McMacCreditCtl_cfgTxCreditThrd][mode];
    }
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacCreditCtl_cfgTxCreditThrd_0_cfgTxCreditThrd_f, cfg_value);

    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_credit_ctl(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_mii_rx_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 mac_idx,
                                    uint8 if_mode, uint8 fec_type)
{
    uint8  fld_num = 0;
    uint8  mode    = 0;
    reg_field_info_t fld_info[3] = {{0}};

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxBuffMaxDepth_f,
                        g_mac_mii_rx_cfg_by_fec_speed[McMacMiiRx_cfgMcMacMiiRxBuffMaxDepth][mode]);

#ifdef EMULATION_ENV
#ifndef PCS_ONLY
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f,  0);
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f, 0);
#endif
#endif

    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_mcpcs_800_en_clk(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[7] = {{0}};

    sal_memset(fld_info, 0xff, 7 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcFecCore0_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800EnClk_enClkMcFecCore0_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcFecCore1_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800EnClk_enClkMcFecCore1_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs400Core0_f, 1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs400Core1_f, 1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs800_f,      1);

    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_en_clk(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_800_tx_phy_cfg(uint8 lchip, uint8 core_id,
                                        uint8 mac_group_id,
                                        uint8 physical_lane_id,
                                        uint8 if_mode,
                                        uint8 fec_type,
                                        uint8 ocs,
                                        uint8 pcs_idx,
                                        uint8 pcs_l_idx)
{
    uint32 cfg_value = 0;
    uint16 core_pll  = 0;
    uint8  mode      = DMPS_MAX_MODE_FEC;
    uint8  fld_num   = 0;
    reg_field_info_t fld_info[7] = {{0}};
    uint8  ocs_pcs_800_tx_async_fifo_credit_thrd[AT_MAX_MODE_FEC] =
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE */
    {4          , 4           , 6           , 6           , 5            , 4            , 4             , 6            , 5          , 5          ,
     10         , 9           , 9           , 9           , 6            , 5            , 5             , 10           , 9         ,
     9          , 9           , 16          , 16          , 16           , 16           , 9             , 9            ,
     16         , 16          , 9           , 9           , 16           , 16           , 16            , 16           , 4};
    uint8  fre900_pcs_800_phy_async_fifo_credit_thrd[AT_MAX_MODE_FEC] =
    {
    /*XFI_NONE,   XFI_FC2112,   XXVG_NONE,    XXVG_FC2112,  XXVG_RS528,    XLG_NONE,      XLG_FC2112,     LG_R2_NONE,    LG_R2_RS528, LG_R2_RS544,
    LG_R1_NONE,   LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272,  CG_R4_NONE,    CG_R4_RS528,   CG_R4_RS544,    CG_R2_NONE,    CG_R2_RS528,
    CG_R2_RS544,  CG_R2_RS272,  CG_R1_RS544,  CG_R1_RS272,  CG_R1_RS544_P, CG_R1_RS272_P, CCG_R4_RS544,   CCG_R4_RS272,
    CCG_R2_RS544, CCG_R2_RS272, CDG_R8_RS544, CDG_R8_RS272, CDG_R4_RS544,  CDG_R4_RS272,  DCCCG_R8_RS544, DCCCG_R8_RS272,NONE*/
     4          , 4           , 7           , 7           , 6            , 4            , 4             , 7            , 6          , 6          ,
     13         , 11          , 11          , 11          , 7            , 6            , 6             , 13           , 11         ,
     11         , 11          , 20          , 20          , 20           , 20           , 11            , 11           ,
     20         , 20          , 11          , 11          , 20           , 20           , 20            , 20           , 0}; /* McPcs800PhyLane_cfgTxAsyncFifoCreditThrd */

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 7 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxPmaWidth_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgPmaWidth][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxLaneFcFecEn_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgFcFecEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxLaneAsyncFifoStartThrd_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgTxLaneAsyncFifoStartThrd][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxBufStartRdThrd_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgTxBufStartRdThrd][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxChanId_f, pcs_idx);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxLaneId_f, pcs_l_idx);
    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
    if (900 == core_pll)
    {
        cfg_value = fre900_pcs_800_phy_async_fifo_credit_thrd[mode];
    }
    else if (CTC_CHIP_SERDES_OCS_MODE_NONE != ocs)
    {
        cfg_value = ocs_pcs_800_tx_async_fifo_credit_thrd[mode];
    }
    else
    {
        cfg_value = g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgTxAsyncFifoCreditThrd][mode];
    }
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxAsyncFifoCreditThrd_f, cfg_value);

    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_tx_phy_lane_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_800_rx_phy_cfg(uint8 lchip, uint8 core_id,
                                        uint8 mac_group_id,
                                        uint16 physical_lane_id,
                                        uint8 if_mode,
                                        uint8 fec_type,
                                        uint8 pcs_idx,
                                        uint8 logical_lane_id)
{
    uint8  fld_num   = 0;
    uint8  mode      = DMPS_MAX_MODE_FEC;
    reg_field_info_t fld_info[6] = {{0}};
    uint8 physical_to_logical[AT_SERDES_NUM_PER_MCMAC] = {0, 2, 4, 6, 1, 3, 5, 7};

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 6 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxPmaWidth_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgPmaWidth][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxLaneBitDemuxEn_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgLaneBitDemuxEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxFcFecEn_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgFcFecEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxRsFecEn_f,
                        g_pcs_800_phy_cfg_by_fec_speed[McPcs800PhyLane_cfgRsFecEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f, pcs_idx);
    if (CTC_CHIP_SERDES_CDG_R8_MODE == if_mode)
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxLogicLaneId_f,
                            physical_to_logical[physical_lane_id]);
    }
    else
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, physical_lane_id, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxLogicLaneId_f,
                            logical_lane_id * 2);
    }
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rx_phy_lane_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_400_rx_fec_chan_map(uint8 lchip, uint8 core_id, uint8 mac_group_id,
                                                    uint8 pcs_half_idx, uint8 pcs_idx,
                                                    uint8 pcs_l_idx, uint8 if_mode)
{
    uint8  fld_num      = 0;
    uint8  inner_pcs_id = pcs_idx + pcs_l_idx;
    uint32 fld_id       = 0;
    reg_field_info_t fld_info[2] = {{0}};

    fld_id = (inner_pcs_id < 2) ? McPcs400RxFecChanMap_cfgFec0Chan0PcsChan_f : McPcs400RxFecChanMap_cfgFec1Chan0PcsChan_f;

    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 2 * (inner_pcs_id % 2),     fld_id, pcs_idx % 4);
    SET_REG_FIELD_INFO(fld_info, fld_num, 2 * (inner_pcs_id % 2) + 1, fld_id, pcs_idx % 4);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_fec_chan_map(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_400_rx_lane_cfg(uint8 lchip, uint8 core_id,
                                        uint8 mac_group_id,
                                        uint8 pcs_half_idx,
                                        uint16 logical_lane_id,
                                        uint8 if_mode,
                                        uint8 fec_type)
{
    uint8  fld_num   = 0;
    uint8  mode      = DMPS_MAX_MODE_FEC;
    reg_field_info_t fld_info[6] = {{0}};

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 6 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, logical_lane_id, McPcs400RxLaneCfg_cfgRxLane_0_cfgRxChanSpeed_f,
                        g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_cfgRxChanSpeed][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, logical_lane_id, McPcs400RxLaneCfg_cfgRxLane_0_cfgRxLaneSpeed_f,
                        g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_cfgRxLaneSpeed][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, logical_lane_id, McPcs400RxLaneCfg_cfgRxLane_0_cfgRxAmInterval_f,
                        g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_cfgRxAmInterval][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, logical_lane_id, McPcs400RxLaneCfg_cfgRxLane_0_cfgRxRsFecEn_f,
                        g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_cfgRxRsFecEn][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, logical_lane_id, McPcs400RxLaneCfg_cfgRxLane_0_cfgRxCwmLockFsmMode_f,
                        g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_cfgRxCwmLockFsmMode][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, logical_lane_id, McPcs400RxLaneCfg_cfgRxLane_0_cfgRxCl161Mode_f,
                        g_pcs_400_rx_lane_cfg_by_fec_speed[McPcs400RxLane_cfgRxCl161Mode][mode]);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_lane_cfg(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_400_rx_chan_cfg(uint8 lchip, uint8 core_id,
                                        uint8 mac_group_id,
                                        uint8 pcs_half_idx,
                                        uint8 pcs_idx,
                                        uint8 if_mode,
                                        uint8 fec_type,
                                        uint8 pcs_num)
{
    uint8  cnt     = 0;
    uint8  fld_num = 0;
    uint8  mode    = DMPS_MAX_MODE_FEC;
    reg_field_info_t fld_info[8] = {{0}};

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400RxChanCfg_cfgRxChan_0_cfgRxFecMode_f,
                        g_pcs_400_rx_chan_cfg_by_fec_speed[McPcs400Rx_cfgRxFecMode][mode]);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400RxChanCfg_cfgRxChan_0_cfgRxFecCwmSfBitsEn_f,
                        g_pcs_400_rx_chan_cfg_by_fec_speed[McPcs400Rx_cfgRxFecCwmSfBitsEn][mode]);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_chan_cfg(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));

    if (CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
    {
        for (cnt = 0; cnt < 8; cnt++)
        {
            sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, cnt % 4, McPcs400RxChanCfg_cfgRxChan_0_cfgRxDskMaxAddr_f,
                                 g_pcs_400_rx_chan_cfg_by_fec_speed[McPcs400Rx_cfgRxDskMaxAddr][mode]);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_chan_cfg(lchip, core_id, 2 * mac_group_id + cnt / 4, fld_num, fld_info));
        }
    }
    else
    {
        sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
        fld_num = 0;
        for (cnt = 0; cnt < pcs_num; cnt++)
        {
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx + cnt, McPcs400RxChanCfg_cfgRxChan_0_cfgRxDskMaxAddr_f,
                                g_pcs_400_rx_chan_cfg_by_fec_speed[McPcs400Rx_cfgRxDskMaxAddr][mode]);
        }
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_chan_cfg(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_400_tx_chan_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id,
                                        uint8 pcs_half_idx, uint8 pcs_idx, uint8 if_mode, uint8 fec_type)
{
    uint8  fld_num = 0;
    uint8  mode    = DMPS_MAX_MODE_FEC;
    reg_field_info_t fld_info[4] = {{0}};

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxCodecSelChan0_f, ((pcs_idx > 1) ? 1 : 0));

    if (CTC_CHIP_SERDES_CG_MODE == if_mode)
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxChan_0_cfg100GCwmMode_f, 0);
    }
    else if ((CTC_CHIP_SERDES_CG_R2_MODE == if_mode) || (CTC_CHIP_SERDES_CG_R1_MODE == if_mode))
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxChan_0_cfg100GCwmMode_f, 1);
    }

    if ((pcs_idx == 0) || (pcs_idx == 2))
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxFecChan0_f, 0);
    }
    else
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxFecChan0_f, 2);
    }

    if ((CTC_CHIP_SERDES_CG_R1_MODE == if_mode) &&
        ((SYS_DMPS_FEC_TYPE_RS544INT == fec_type) || (SYS_DMPS_FEC_TYPE_RS272INT == fec_type)))
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxChan_0_cfgCl161Mode_f, 1);
    }
    else
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs400TxChanCfg_cfgTxChan_0_cfgCl161Mode_f, 0);
    }

    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_tx_chan_cfg(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_mcpcs_400_rx_chan_map(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[4] = {{0}};

    /* cfg cfgPcsChan0-3FecChan */
    sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 2);
    SET_REG_FIELD_INFO(fld_info, fld_num, 2, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 3, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 2);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_fec_chan_map(lchip, core_id, 2 * mac_group_id,fld_num, fld_info));

    sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 2);
    SET_REG_FIELD_INFO(fld_info, fld_num, 2, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 3, McPcs400RxFecChanMap_cfgPcsChan0FecChan_f, 2);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_fec_chan_map(lchip, core_id, 2 * mac_group_id + 1, fld_num, fld_info));

    /* cfgPcsChan0-3CodecSel */
    fld_num = 0;
    sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 2, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 3, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_fec_chan_map(lchip, core_id, 2 * mac_group_id, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 4 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 2, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 3, McPcs400RxFecChanMap_cfgPcsChan0CodecSel_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_rx_fec_chan_map(lchip, core_id, 2 * mac_group_id + 1, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_400_fec_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id,
                                        uint8 pcs_half_idx, uint8 if_mode, uint8 fec_type, uint32 value)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs400McFecCfg_cfg2In1En_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_fec_cfg(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_400_pma_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id,
                                        uint8 pcs_half_idx, uint8 idx, uint8 if_mode, uint8 fec_type, uint32 value)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, idx, McPcs400PmaCfg_cfgTxAsyncFifoUnderrunEnLane0_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_pma_cfg(lchip, core_id, 2 * mac_group_id + pcs_half_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 value)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacMacTxCfg_cfgMacMuxMcMacTxEnDisable_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_tx_cal_walkend(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 value)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1] = {{0}};

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgTxWalkerEnd_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_cal_ctrl(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

uint8
_sys_at_mac_group_is_full_used(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  cnt        = 0;
    uint8  lane_full  = TRUE;
    uint16 mac_id     = 0;
    uint16 dport      = 0;
    uint16 speed_mode = 0;
    uint16 speed_sum  = 0;
    uint16 core_pll   = 0;
    uint32 speed_max  = 0;
    uint32 speed      = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
    speed_max = (1350 == core_pll) ? SYS_AT_MAX_BANDWIDTH_PER_MCMAC : (SYS_AT_MAX_BANDWIDTH_PER_MCMAC / 2);
    for (cnt = 0; cnt < AT_MAC_ID_NUM_PER_MCMAC; cnt++)
    {
        mac_id  = core_id * AT_MAC_NUM_PER_CORE + mac_group_id * AT_MAC_ID_NUM_PER_MCMAC + cnt;
        if ((CTC_E_NONE != sys_usw_dmps_db_get_single_relative_id(lchip, DMPS_DB_TYPE_MAC, mac_id, DMPS_DB_TYPE_PORT, &dport))
            || (DMPS_INVALID_VALUE_U16 == dport))
        {
            lane_full = FALSE;
        }

        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_MAC, mac_id));
        SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID, mac_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);

        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
        speed = ((speed > 0) && (speed < 50)) ? 50 : speed;
        speed_sum += speed;
    }

    if ((!lane_full) && (speed_sum < (speed_max / 2)))
    {
        return FALSE;
    }
    else
    {
        return TRUE;
    }
}

#if 0

int32
_sys_at_mac_get_half_speed_list(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 half_idx, uint32 speed_list[])
{
    uint8  cnt        = 0;
    uint8  is_ock     = 0;
    uint16 mac_id     = 0;
    uint16 speed_mode = 0;
    uint32 speed_sum  = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    for (cnt = 0; cnt < (AT_MAC_ID_NUM_PER_MCMAC / 2); cnt++)
    {
        mac_id  = core_id * AT_MAC_NUM_PER_CORE + mac_group_id * AT_MAC_ID_NUM_PER_MCMAC + cnt + half_idx * (AT_MAC_ID_NUM_PER_MCMAC / 2);
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_MAC, mac_id));
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID, mac_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,         is_ock);
        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed_list[cnt]);
        speed_list[cnt] = is_ock ? ((200 == speed_list[cnt]) ? 215 :
                                    (100 == speed_list[cnt]) ? 110 :
                                    (50  == speed_list[cnt]) ? 55  : speed_list[cnt]) : speed_list[cnt];
        speed_list[cnt] = (40 == speed_list[cnt]) ? 50 : ((10 == speed_list[cnt]) ? 25 : speed_list[cnt]);
        speed_sum += speed_list[cnt];
    }

    if (speed_sum > SYS_AT_MAX_BANDWIDTH_PER_MCMAC / 2)
    {
        speed_sum = 0;
        for (cnt = 0; cnt < (AT_MAC_ID_NUM_PER_MCMAC / 2); cnt++)
        {
            mac_id  = core_id * AT_MAC_NUM_PER_CORE + mac_group_id * AT_MAC_ID_NUM_PER_MCMAC + 2 * cnt + half_idx;
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID, mac_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);
            SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed_list[cnt]);
            speed_list[cnt] = (40 == speed_list[cnt]) ? 50 : ((10 == speed_list[cnt]) ? 25 : speed_list[cnt]);
            speed_sum += speed_list[cnt];
        }
    }

    speed_list[AT_MAC_ID_NUM_PER_MCMAC / 2 - 1] = SYS_AT_MAX_BANDWIDTH_PER_MCMAC / 2 - (speed_sum - speed_list[AT_MAC_ID_NUM_PER_MCMAC / 2 - 1]);

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_tx_cal_1to2(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  is_bak     = 0;
    uint8  fld_num    = 0;
    uint8  half_idx   = 0;
    uint8  p_error    = 0;
    uint8  loop       = 0;
    uint8  cnt        = 0;
    uint16 p_walkend  = 0;
    uint32 speed_list[AT_MAC_ID_NUM_PER_MCMAC / 2] = {0};
    uint16 cal[SYS_AT_MAX_MAC_CAL_ENTRY]       = {0};
    uint16 p_cal[SYS_AT_MAX_MAC_CAL_ENTRY / 2] = {0};
    reg_field_info_t fld_info[2] = {{0}};

    SET_REG_SOURCE_FIELD_INFO(fld_info, 0, McMacCalCtrl_cfgTxCalEntrySel_f);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_cal_ctrl(lchip, core_id, mac_group_id, 1, fld_info));
    is_bak = fld_info[0].value;

    for (half_idx = 0; half_idx < 2; half_idx++)
    {
        sal_memset(speed_list, 0, (AT_MAC_ID_NUM_PER_MCMAC / 2)  * sizeof(uint32));
        sal_memset(p_cal,      0, (SYS_AT_MAX_MAC_CAL_ENTRY / 2) * sizeof(uint16));
        CTC_ERROR_RETURN(_sys_at_mac_get_half_speed_list(lchip, core_id, mac_group_id, half_idx, speed_list));
        CTC_ERROR_RETURN(_sys_at_datapath_common_calendar(SYS_AT_MAX_MAC_CAL_ENTRY / 2,
                            AT_MAC_ID_NUM_PER_MCMAC / 2, speed_list, &p_error, &p_walkend, p_cal));
        SYS_CONDITION_CONTINUE(0 == p_walkend);
        loop = (SYS_AT_MAX_MAC_CAL_ENTRY / 2) / (p_walkend + 1);
        for (cnt = 1; cnt < loop; cnt++)
        {
            sal_memcpy((p_cal + (p_walkend + 1) * cnt), p_cal, (p_walkend + 1) * sizeof(uint16));
        }

        for (cnt = 0; cnt < (SYS_AT_MAX_MAC_CAL_ENTRY / 2); cnt++)
        {
            cal[2 * cnt + half_idx] = p_cal[cnt] + half_idx * (AT_MAC_ID_NUM_PER_MCMAC / 2);
        }
    }

    if (is_bak)
    {
        for (cnt = 0; cnt < SYS_AT_MAX_MAC_CAL_ENTRY; cnt++)
        {
            fld_num = 0;
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacTxCal_calEntry_f, cal[cnt]);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_cal(lchip, core_id, mac_group_id, cnt, fld_num, fld_info));
        }
    }
    else
    {
        for (cnt = 0; cnt < SYS_AT_MAX_MAC_CAL_ENTRY; cnt++)
        {
            fld_num = 0;
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacTxCalBak_calEntry_f, cal[cnt]);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_cal_bak(lchip, core_id, mac_group_id, cnt, fld_num, fld_info));
        }
    }

    fld_num = 0;
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgTxCalEntrySel_f, (is_bak ? 0 : 1));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, (is_bak ? McMacCalCtrl_cfgTxWalkerEnd_f : McMacCalCtrl_cfgTxWalkerEndBak_f), SYS_AT_MAX_MAC_CAL_ENTRY);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_cal_ctrl(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_rx_cal_agg_1to2(uint8 lchip, uint8 core_id, uint8 mac_group_id)
#endif
int32
_sys_at_mac_set_mcmac_rx_cal_agg_1to2(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 is_txqm_agg)
{
    uint8  idx        = 0;
    uint8  speed_mode = 0;
    uint8  p_error    = 0;
    uint8  is_bak     = 0;
    uint8  cnt        = 0;
    uint8  fld_num    = 0;
    uint16 mac_id     = 0;
    uint16 p_walkend  = 0;
    uint16 core_pll   = 0;
    uint32 speed_max  = 0;
    uint32 speed_sum  = 0;
    uint16 p_cal[SYS_AT_MAX_MAC_CAL_ENTRY]     = {0};
    uint8  ock[AT_MAC_ID_NUM_PER_MCMAC]        = {0};
    uint32 speed[AT_MAC_ID_NUM_PER_MCMAC]      = {0};
    uint32 speed_list[AT_MAC_ID_NUM_PER_MCMAC] = {0};
    sys_dmps_db_upt_info_t port_info           = {0};
    reg_field_info_t fld_info[2]               = {{0}};

    /* 1. get speed */
    for (idx = 0; idx < AT_MAC_ID_NUM_PER_MCMAC; idx++)
    {
        mac_id  = core_id * AT_MAC_NUM_PER_CORE + mac_group_id * AT_MAC_ID_NUM_PER_MCMAC + idx;

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,               mac_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,         ock[idx]);

        SYS_AT_SPEED_MODE_TO_SPEED_VALUE(speed_mode, speed[idx]);
        speed[idx] = (40 == speed[idx]) ? 50 : ((10 == speed[idx]) ? 25 : speed[idx]);
    }

    /* 2. update speed for overclock */
    for (idx = 0; idx < AT_MAC_ID_NUM_PER_MCMAC; idx++)
    {
        speed_list[idx] = ock[idx] ?
                             ((400 == speed[idx]) ? 425 :
                              (200 == speed[idx]) ? 215 :
                              (100 == speed[idx]) ? 110 :
                              (50  == speed[idx]) ? 55  : speed[idx]) : speed[idx];
        speed_sum += speed_list[idx];
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1));
    speed_max = (1350 == core_pll) ? SYS_AT_MAX_BANDWIDTH_PER_MCMAC : (SYS_AT_MAX_BANDWIDTH_PER_MCMAC / 2);
    /* 3. check if speed_sum > speed_max / 2, ignore overclock */
    if (speed_sum > (speed_max / 2))
    {
        sal_memcpy(speed_list, speed, AT_MAC_ID_NUM_PER_MCMAC*sizeof(uint32));
    }

    if (is_txqm_agg)
    {
        speed_list[AT_MAC_ID_NUM_PER_MCMAC - 1] += ((speed_max > speed_sum) ? (speed_max - speed_sum) : 0);
    }

    /* get calendar */
    CTC_ERROR_RETURN(_sys_at_datapath_common_calendar(SYS_AT_MAX_MAC_CAL_ENTRY,
                            AT_MAC_ID_NUM_PER_MCMAC, speed_list, &p_error, &p_walkend, p_cal));

    if (p_error)
    {
        return CTC_E_INVALID_CONFIG;
    }

    /* config register */
    SET_REG_SOURCE_FIELD_INFO(fld_info, 0, McMacCalCtrl_cfgRxCalEntrySel_f);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_cal_ctrl(lchip, core_id, mac_group_id, 1, fld_info));
    is_bak = fld_info[0].value;

    if (is_bak)
    {
        for (cnt = 0; cnt < SYS_AT_MAX_MAC_CAL_ENTRY; cnt++)
        {
            fld_num = 0;
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacRxCal_calEntry_f, p_cal[cnt]);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_cal(lchip, core_id, mac_group_id, cnt, fld_num, fld_info));
        }
    }
    else
    {
        for (cnt = 0; cnt < SYS_AT_MAX_MAC_CAL_ENTRY; cnt++)
        {
            fld_num = 0;
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacRxCalBak_calEntry_f, p_cal[cnt]);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_cal_bak(lchip, core_id, mac_group_id, cnt, fld_num, fld_info));
        }
    }

    fld_num = 0;
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacCalCtrl_cfgRxCalEntrySel_f, (is_bak ? 0 : 1));
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, (is_bak ? McMacCalCtrl_cfgRxWalkerEnd_f : McMacCalCtrl_cfgRxWalkerEndBak_f), p_walkend);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_cal_ctrl(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcmac_config(uint8 lchip, uint16 mac_id)
{
    uint8  idx                = 0;
    uint8  mac_group_id       = 0;
    uint8  remote_mac_group   = 0;
    uint8  core_id            = 0;
    uint8  serdes_num         = 0;
    uint8  mac_idx            = 0;
    uint8  if_mode            = 0;
    uint8  logic_lane_id      = 0;
    uint8  fec_type           = 0; /*SYS_DMPS_FEC_TYPE_MAX*/
    uint8  ocs                = 0;
    uint8  physical_lane_id   = 0;
    uint8  step               = 0;
    uint8  entry_num          = 0;
    uint8  entry_lane         = 0;
    uint16 core_pll           = 0;
    uint16 remote_lsd         = 0;
    uint32 serdes_speed       = 0;
    uint32 speed_sum          = 0;
    uint32 remote_speed_sum   = 0;
    uint16 logic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};
    uint8  mac_entry_map[AT_ENTRY_NUM_PER_MCMAC] = {0, 4, 2, 6, 1, 5, 3, 7};
    uint8  cal_per_mac[AT_MAC_ID_NUM_PER_MCMAC]  = {0, 1, 2, 3, 4, 5, 6, 7};
    uint8  mac_entry_map_1to2[2 * AT_ENTRY_NUM_PER_MCMAC] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};
    uint8  cal_per_mac_1to2[2 * AT_MAC_ID_NUM_PER_MCMAC]  = {0, 3, 1, 3,  2, 3,  3, 3,  4, 7, 5, 7,  6, 7,  7, 7};
    sys_dmps_db_upt_info_t port_info             = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,               mac_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_LANE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,       serdes_speed);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,    mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,         ocs);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_LANE_ID,     physical_lane_id);   

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_MAC, mac_id, DMPS_DB_TYPE_LSD, &serdes_num, logic_serdes));
    SYS_CONDITION_RETURN(!SYS_AT_IS_NW_SERDES(logic_serdes[0]), CTC_E_INVALID_PORT);

    if (0 == serdes_speed)
    {
        if_mode    = CTC_CHIP_SERDES_NONE_MODE;
        fec_type   = SYS_DMPS_FEC_TYPE_NONE;
    }
    else
    {
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,    if_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE,   fec_type);
    }

    SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, serdes_num);
    core_id = SYS_AT_GET_CORE_BY_NW_SERDES(logic_serdes[0]);

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp,"// ------ MAC per port config, mac %d ----------------\n", mac_id);

    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_rx_cfg(lchip, core_id, mac_group_id, mac_idx, if_mode, fec_type));
    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cfg(lchip, core_id, mac_group_id, mac_idx, if_mode, fec_type));
    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_credit_ctl_cfg(lchip, core_id, mac_group_id, mac_idx, if_mode, fec_type, ocs));
    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mii_rx_cfg(lchip, core_id, mac_group_id, mac_idx, if_mode, fec_type));
    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mii_tx_cfg(lchip, core_id, mac_group_id, mac_idx, if_mode, fec_type, ocs));
    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_pause_tx_ctl(lchip, core_id, mac_group_id, mac_idx, if_mode, fec_type));

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
    serdes_num = (0 == serdes_num) ? 1 : serdes_num;

    remote_mac_group = SYS_AT_GET_REMOTE_GROUP_IN_1TO2_MAC_AGG(lchip, mac_group_id);
    if ((900 == core_pll) && (SYS_AT_USELESS_ID8 != remote_mac_group))
    {
        for (idx = 0; idx < AT_MAC_ID_NUM_PER_MCMAC; idx++)
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,   logic_serdes[0] / AT_MAC_ID_NUM_PER_MCMAC * AT_MAC_ID_NUM_PER_MCMAC + idx);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED, serdes_speed);
            speed_sum += serdes_speed;
        }

        remote_lsd = core_id * AT_MAC_NUM_PER_CORE + remote_mac_group * AT_MAC_ID_NUM_PER_MCMAC;
        for (idx = 0; idx < AT_MAC_ID_NUM_PER_MCMAC; idx++)
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,   remote_lsd + idx);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED, serdes_speed);
            remote_speed_sum += serdes_speed;
        }

        if ((0 == speed_sum) && (0 == remote_speed_sum))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, mac_group_id,     0));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, remote_mac_group, 0));
        }
        else if ((0 == speed_sum) && (0 != remote_speed_sum))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, mac_group_id,     0));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, remote_mac_group, 1));
        }
        else if ((0 != speed_sum) && (0 == remote_speed_sum))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, mac_group_id,     1));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, remote_mac_group, 0));
        }
        else if ((0 != speed_sum) && (0 != remote_speed_sum))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, mac_group_id,     0));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_mux_mac_tx_en_disable(lchip, core_id, remote_mac_group, 0));
        }
    }

    /* get mac cal by speed_mode */
    if (SYS_AT_IS_1TO2_GROUP(lchip, mac_group_id))
    {
#if 1
        if (SYS_AT_IS_1TO2_MAC_AGG_GROUP(lchip, mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_rx_cal_agg_1to2(lchip, core_id, mac_group_id, FALSE));
        }
        else if (SYS_AT_IS_1TO2_TXQM_AGG_GROUP(lchip, mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_rx_cal_agg_1to2(lchip, core_id, mac_group_id, TRUE));
        }

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,         logic_serdes[0]);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_LSD_LANE_ID);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_LSD_LANE_ID,     logic_lane_id);

        CTC_ERROR_RETURN(_sys_at_mac_get_cal_by_speed(lchip, 2 * mac_idx, if_mode, cal_per_mac_1to2, &step));
        entry_num = (2 * serdes_num > step) ? (2 * serdes_num) : step;

        for (idx = 0; idx < entry_num; idx++)
        {
            entry_lane = 2 * logic_lane_id + idx;
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal(lchip, core_id, mac_group_id,
                mac_entry_map_1to2[entry_lane], cal_per_mac_1to2[entry_lane]));
        }
        if (_sys_at_mac_group_is_full_used(lchip, core_id, mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal_walkend(lchip, core_id, mac_group_id, 15));
        }
        else
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal_walkend(lchip, core_id, mac_group_id, 13));
        }
#else
        CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal_1to2(lchip, core_id, mac_group_id));
#endif
    }

    CTC_ERROR_RETURN(_sys_at_mac_get_cal_by_lane(lchip, mac_idx, if_mode, cal_per_mac));

    /* config mac per lane */
    for(idx = 0; idx < serdes_num; idx++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,         logic_serdes[idx]);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_LSD_LANE_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_LANE_ID);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_LSD_LANE_ID,     logic_lane_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_LANE_ID,     physical_lane_id);

        if (!SYS_AT_IS_1TO2_GROUP(lchip, mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_rx_cal(lchip, core_id, mac_group_id,
                mac_entry_map[logic_lane_id], cal_per_mac[logic_lane_id]));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal(lchip, core_id, mac_group_id,
                mac_entry_map[logic_lane_id], cal_per_mac[logic_lane_id]));
        }

#ifdef PCS_ONLY
        if ((mac_group_id == 0) || (mac_group_id == 1))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_chan_lane_cfg(lchip, core_id, mac_group_id, logic_lane_id, mac_idx));
        }
        else
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_chan_lane_cfg(lchip, core_id, mac_group_id, physical_lane_id, mac_idx));
        }
#else
        CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_chan_lane_cfg(lchip, core_id, mac_group_id, physical_lane_id, mac_idx));
#endif
    }
    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mcpcs_config(uint8 lchip, uint16 mac_id)
{
    uint8  idx              = 0;
    uint8  mac_group_id     = 0;
    uint8  core_id          = 0;
    uint8  serdes_num       = 0;
    uint8  pcs_idx          = 0;
    uint8  pcs_lane         = 0;
    uint8  logic_lane       = 0;
    uint8  physic_lane      = 0;
    uint8  if_mode          = 0;
    uint8  fec_type         = 0; /*sys_usw_dmps_fec_type_t*/
    uint8  ocs              = 0;
    uint8  chip_type        = SYS_AT_GET_CHIP_TYPE(lchip);
    uint32 serdes_speed     = 0;
    uint16 logic_serdes[DMPS_MAX_NUM_PER_MODULE]  = {0};
    sys_dmps_db_upt_info_t port_info              = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,               mac_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,       serdes_speed);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,    mac_group_id);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_MAC, mac_id, DMPS_DB_TYPE_LSD, &serdes_num, logic_serdes));
    SYS_CONDITION_RETURN(!SYS_AT_IS_NW_SERDES(logic_serdes[0]), CTC_E_INVALID_PORT);

    if (0 == serdes_speed)
    {
        if_mode    = CTC_CHIP_SERDES_NONE_MODE;
        fec_type   = SYS_DMPS_FEC_TYPE_NONE;
    }
    else
    {
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,    if_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE,   fec_type);
    }

    pcs_lane = pcs_idx;
    core_id  = SYS_AT_GET_CORE_BY_NW_SERDES(logic_serdes[0]);
    SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, serdes_num);

    serdes_num = (0 == serdes_num) ? 1 : serdes_num;
    for(idx = 0; idx < serdes_num; idx++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,         logic_serdes[idx]);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_LANE_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_LSD_LANE_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_LANE_ID,     physic_lane);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_LSD_LANE_ID,     logic_lane);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,         ocs);

        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_rx_fec_chan_map(lchip, core_id, mac_group_id,
            pcs_lane / 4, pcs_idx % 4, idx % 4, if_mode));

#ifdef PCS_ONLY
        if ((mac_group_id == 0) || (mac_group_id == 1))
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES,        logic_serdes[idx]);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,         ocs);
            /* config McPcs800RxPhyLaneCfg */
            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_800_tx_phy_cfg(lchip, core_id, mac_group_id, logic_lane,
                if_mode, fec_type, ocs, pcs_idx, idx));
            /* config McPcs800TxPhyLaneCfg */
            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_800_rx_phy_cfg(lchip, core_id, mac_group_id, logic_lane,
                if_mode, fec_type, pcs_idx, logic_lane));
        }
        else
        {
            /* config McPcs800RxPhyLaneCfg */
            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_800_tx_phy_cfg(lchip, core_id, mac_group_id, physic_lane,
                if_mode, fec_type, ocs, pcs_idx, idx));
            /* config McPcs800TxPhyLaneCfg */
            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_800_rx_phy_cfg(lchip, core_id, mac_group_id, physic_lane,
                if_mode, fec_type, pcs_idx, logic_lane));
        }
#else
        /* config McPcs800RxPhyLaneCfg */
        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_800_tx_phy_cfg(lchip, core_id, mac_group_id, physic_lane,
            if_mode, fec_type, ocs, pcs_idx, idx));
        /* config McPcs800TxPhyLaneCfg */
        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_800_rx_phy_cfg(lchip, core_id, mac_group_id, physic_lane,
            if_mode, fec_type, pcs_idx, logic_lane));
#endif

        /* config McPcs400RxLaneCfg */
        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_rx_lane_cfg(lchip, core_id, mac_group_id,
            pcs_lane / 4, 2 * (logic_lane % 4), if_mode, fec_type));
        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_rx_lane_cfg(lchip, core_id, mac_group_id,
            pcs_lane / 4, 2 * (logic_lane % 4) + 1, if_mode, fec_type));

        /* config McPcs400RxChanCfg0 or McPcs400RxChanCfg1 */
        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_rx_chan_cfg(lchip, core_id, mac_group_id,
            pcs_lane / 4, pcs_lane % 4, if_mode, fec_type, 1));
        /* config McPcs400TxChanCfg0 or McPcs400TxChanCfg1 */
        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_tx_chan_cfg(lchip, core_id, mac_group_id,
            pcs_lane / 4, pcs_lane % 4, if_mode, fec_type));

        /* config McPcs400McFecCfg_cfg2ln1En */
        if (CTC_CHIP_SERDES_CCG_R4_MODE == if_mode)
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_fec_cfg(lchip, core_id, mac_group_id,
                pcs_lane / 4, if_mode, fec_type, 0));
        }
        else
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_fec_cfg(lchip, core_id, mac_group_id,
                pcs_lane / 4, if_mode, fec_type, 1));
        }

        if (SYS_AT_IS_1PP(chip_type))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id,
                physic_lane / 4, physic_lane % 4, HssLaneCfg_cfgForcePmaReady4PcsEnLane, 1));
            CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id,
                physic_lane / 4, physic_lane % 4, HssLaneCfg_cfgForcePmaReady4PcsValueLane, 1));

            CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_pma_cfg(lchip, core_id, mac_group_id,
                pcs_lane / 4, pcs_lane % 4, if_mode, fec_type, 1));
        }

#if defined(PCS_ONLY)  || defined(EMULATOR_ENV)
        /* only config in Emulation */
        CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id,
            physic_lane / 4, physic_lane % 4, HssLaneCfg_cfgForcePmaReady4PcsEnLane, 1));
        CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id,
            physic_lane / 4, physic_lane % 4, HssLaneCfg_cfgForcePmaReady4PcsValueLane, 1));

        CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_400_pma_cfg(lchip, core_id, mac_group_id,
            pcs_lane / 4, pcs_lane % 4, if_mode, fec_type, 1));
#endif
        pcs_lane++;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mchata_config(uint8 lchip, uint16 mac_id)
{
    uint8  idx          = 0;
    uint8  mac_idx      = 0;
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  serdes_num   = 0;
    uint8  if_mode      = 0;
    uint8  fec_type     = 0; /*SYS_DMPS_FEC_TYPE_MAX*/
    uint8  physic_lane  = 0;
    uint8  logic_lane   = 0;
    uint8  mode         = 0;
    uint8  fld_num      = 0;
    uint32 serdes_speed = 0;
    reg_field_info_t fld_info[8] = {{0}};
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};
    sys_dmps_db_upt_info_t port_info              = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,               mac_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,       serdes_speed);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,    mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mac_idx);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_MAC, mac_id, DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));
    SYS_CONDITION_RETURN(!SYS_AT_IS_NW_SERDES(physic_serdes[0]), CTC_E_INVALID_PORT);

    if (0 == serdes_speed)
    {
        if_mode    = CTC_CHIP_SERDES_NONE_MODE;
        fec_type   = SYS_DMPS_FEC_TYPE_NONE;
    }
    else
    {
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,    if_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE,   fec_type);
    }

    core_id = SYS_AT_GET_CORE_BY_NW_SERDES(physic_serdes[0]);

    CTC_ERROR_RETURN(_sys_usw_mac_get_mode_with_fec(lchip, if_mode, fec_type, &mode));

    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataRxCfg_cfgHataRsFecMode0_f,
                            g_hata_rx_cfg_by_fec_speed[McHataRsCfg_Mode][mode]);
    CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    for(idx = 0; idx < serdes_num; idx++)
    {
        fld_num = 0;
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES,        physic_serdes[idx]);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_LANE_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_LSD_LANE_ID);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_LANE_ID,     physic_lane);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_LSD_LANE_ID,     logic_lane);

        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McHataTxPhyLaneToChanMap_phyLaneToChanMap_f, logic_lane);
        CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_tx_phy_lane2chan_map(lchip, core_id, mac_group_id, physic_lane, fld_num, fld_info));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_nw_config_by_mac_id(uint8 lchip, uint16 mac_id)
{
    CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_config(lchip, mac_id));
    CTC_ERROR_RETURN(_sys_at_mac_set_mcpcs_config(lchip, mac_id));

    if (g_at_hata_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_mchata_config(lchip, mac_id));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmii_config(uint8 lchip, uint16 dport)
{
    uint32 value               = 0;
    uint32 value1              = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint16 step                = 0;
    uint8  sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  speed_mode          = 0;
    uint8  core_id             = 0;
    uint8  port_idx            = 0;
    uint8  fld_num             = 0;
    reg_field_info_t fld_info[15]     = {{0}};
    sys_dmps_db_upt_info_t port_info  = {0};
    CpuMacClockTreeCfg_m       clk_tree_cfg;
    CpuMacCtlCfg_m ctl_cfg;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,        port_idx);

    sgmac_idx  = mii_idx;

    /* cfg CpuMacClockTreeCfg */
    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    step   = CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f - CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f - CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f - CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f;
    fld_id = CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    fld_id = CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f - CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f;
    fld_id = CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f - CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f;
    fld_id = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    /* cfg CpuMacCtlCfg */
    tbl_id = CpuMacCtlCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    step   = CpuMacCtlCfg_cfgPort1Map_f - CpuMacCtlCfg_cfgPort0Map_f;
    fld_id = CpuMacCtlCfg_cfgPort0Map_f + port_idx * step;
    value  = pcs_idx;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &ctl_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    /* cfg sgmac Rx/Tx*/
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0));
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, 3);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiXauiMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiRXauiMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiQsgmiiMode_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, 0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg per Share Mii*/
    sal_memset(fld_info, 0xff, 15 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFXMode0_f,            0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    4);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      0x3fff);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxRsFecEn0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeedRx0_f,           0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleSlot0_f,      0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f,   0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f,   1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, 0x60);
    switch(speed_mode)
    {
        case SYS_PORT_SPEED_2G5:
            value  = 3;
            value1 = 0;
            break;
        case SYS_PORT_SPEED_1G:
            value  = 2;
            value1 = 0;
            break;
            case SYS_PORT_SPEED_100M:
            value  = 1;
            value1 = 9;
            break;
        case SYS_PORT_SPEED_10M:
            value  = 0;
            value1 = 99;
            break;
        default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"error port speed mode: %d \n", speed_mode);
            return CTC_E_INVALID_PARAM;
    }
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeed0_f,          value);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f, value1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,    value1);
    /*link filter*/
    value = 1;
#ifdef AT_SERDES_SIM
    value = 0;
#endif
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mii_idx, fld_num, fld_info));

    /* additional integrity config */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsDsfCfg_cfgDsfDepth0_f, 31);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_dsf_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg SharedPcsCfg */
    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_cgMode_f,          0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_xlgMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_fxMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_lgMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_xxvgMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeRx0_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeTx0_f,    1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* shared_pcs_serdes_cfg */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, 80);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /*parallelizing check*/
    sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f,      80);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f, 1);
#ifdef AT_SERDES_SIM
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anEnable0_f,          0);
#endif
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_xfi_config(uint8 lchip, uint16 dport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint16 step                = 0;
    uint8  sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  core_id             = 0;
    uint8  port_idx            = 0;
    uint8  fld_num             = 0;
    reg_field_info_t fld_info[15]     = {{0}};
    sys_dmps_db_upt_info_t port_info  = {0};
    CpuMacClockTreeCfg_m       clk_tree_cfg;
    CpuMacCtlCfg_m ctl_cfg;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,        port_idx);

    sgmac_idx  = mii_idx;

    /* cfg CpuMacClockTreeCfg */
    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    step   = CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f - CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f - CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f - CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f;
    fld_id = CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    fld_id = CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f - CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f;
    fld_id = CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f - CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f;
    fld_id = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f + pcs_idx * step;
    value  = 2;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    /* cfg CpuMacCtlCfg */
    tbl_id = CpuMacCtlCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    step   = CpuMacCtlCfg_cfgPort1Map_f - CpuMacCtlCfg_cfgPort0Map_f;
    fld_id = CpuMacCtlCfg_cfgPort0Map_f + port_idx * step;
    value  = pcs_idx;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &ctl_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    /* cfg sgmac Rx/Tx*/
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0));
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0));
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiXauiMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiRXauiMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiQsgmiiMode_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg per Share Mii*/
    sal_memset(fld_info, 0xff, 10 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFXMode0_f,            0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    16);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    17);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      0x3fff);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxRsFecEn0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeedRx0_f,           5);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeed0_f,             5);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mii_idx, fld_num, fld_info));

#if 0
    /* additional integrity config */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsDsfCfg_cfgDsfDepth0_f, 31);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_dsf_cfg(lchip, core_id, 0, fld_num, fld_info));
#endif

    /* cfg SharedPcsCfg */
    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_cgMode_f,          0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_xlgMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_fxMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_lgMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_xxvgMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeRx0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeTx0_f,    0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));

#if 0
    /* shared_pcs_serdes_cfg */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, 80);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /*parallelizing check disable*/
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));
#endif
    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_xlg_config(uint8 lchip, uint16 dport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint16 step                = 0;
    uint8  sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  core_id             = 0;
    uint8  port_idx            = 0;
    uint8  fld_num             = 0;
    reg_field_info_t fld_info[15]     = {{0}};
    sys_dmps_db_upt_info_t port_info  = {0};
    CpuMacCtlCfg_m             ctl_cfg;
    CpuMacClockTreeCfg_m       clk_tree_cfg;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,        port_idx);

    sgmac_idx  = mii_idx;

    /* cfg CpuMacClockTreeCfg */
    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    step   = CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f - CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f - CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f - CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f;
    fld_id = CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    fld_id = CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f - CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f;
    fld_id = CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f - CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f;
    fld_id = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f + pcs_idx * step;
    value  = 2;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    /* cfg CpuMacCtlCfg */
    tbl_id = CpuMacCtlCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    step   = CpuMacCtlCfg_cfgPort1Map_f - CpuMacCtlCfg_cfgPort0Map_f;
    fld_id = CpuMacCtlCfg_cfgPort0Map_f + port_idx * step;
    value  = pcs_idx;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &ctl_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    /* cfg sgmac Rx/Tx*/
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiXauiMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiRXauiMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiQsgmiiMode_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg per Share Mii*/
    sal_memset(fld_info, 0xff, 10 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFXMode0_f,            0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    16);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    17);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      0x3fff);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxRsFecEn0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeedRx0_f,           8);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeed0_f,             8);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mii_idx, fld_num, fld_info));

#if 0
    /* additional integrity config */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsDsfCfg_cfgDsfDepth0_f, 31);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_dsf_cfg(lchip, core_id, 0, fld_num, fld_info));
#endif

    /* cfg SharedPcsCfg */
    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_cgMode_f,          0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_xlgMode_f,         1);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_fxMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_lgMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_xxvgMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeRx0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeTx0_f,    0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));

#if 0
    /* shared_pcs_serdes_cfg */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, 80);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /*parallelizing check disable*/
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));
#endif
    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_xxvg_config(uint8 lchip, uint16 dport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint16 step                = 0;
    uint8  sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  core_id             = 0;
    uint8  port_idx            = 0;
    uint8  fld_num             = 0;
    reg_field_info_t fld_info[15]     = {{0}};
    sys_dmps_db_upt_info_t port_info  = {0};
    CpuMacClockTreeCfg_m       clk_tree_cfg;
    CpuMacCtlCfg_m             ctl_cfg;
    //CpuMacClockTreeCfg_m       clk_tree_cfg;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,        port_idx);

    sgmac_idx  = mii_idx;

    /* cfg CpuMacClockTreeCfg */
    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    step   = CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f - CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f - CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f - CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f;
    fld_id = CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    fld_id = CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f - CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f;
    fld_id = CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f - CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f;
    fld_id = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f + pcs_idx * step;
    value  = 3;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    /* cfg CpuMacCtlCfg */
    tbl_id = CpuMacCtlCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    step   = CpuMacCtlCfg_cfgPort1Map_f - CpuMacCtlCfg_cfgPort0Map_f;
    fld_id = CpuMacCtlCfg_cfgPort0Map_f + port_idx * step;
    value  = pcs_idx;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &ctl_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    /* cfg sgmac Rx/Tx*/
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0));
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0));
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiXauiMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiRXauiMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiQsgmiiMode_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 10 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFXMode0_f,            0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    32);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      0x3fff);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxRsFecEn0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeedRx0_f,           7);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeed0_f,             7);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mii_idx, fld_num, fld_info));

#if 0
    /* additional integrity config */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsDsfCfg_cfgDsfDepth0_f, 31);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_dsf_cfg(lchip, core_id, 0, fld_num, fld_info));
#endif

    /* cfg SharedPcsCfg */
    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_cgMode_f,          0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_xlgMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_fxMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_lgMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_xxvgMode0_f,       1);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeRx0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeTx0_f,    0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));

#if 0
    /* shared_pcs_serdes_cfg */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, 80);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /*parallelizing check disable*/
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));
#endif
    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_lg_config(uint8 lchip, uint16 dport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint16 step                = 0;
    uint8  sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  core_id             = 0;
    uint8  port_idx            = 0;
    uint8  fld_num             = 0;
    reg_field_info_t fld_info[15]     = {{0}};
    sys_dmps_db_upt_info_t port_info  = {0};
    CpuMacCtlCfg_m             ctl_cfg;
    CpuMacClockTreeCfg_m       clk_tree_cfg;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,         mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,        port_idx);

    sgmac_idx  = mii_idx;

    /* cfg CpuMacClockTreeCfg */
    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    step   = CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f - CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f - CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f - CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f;
    fld_id = CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    fld_id = CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f - CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f;
    fld_id = CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f - CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f;
    fld_id = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f + pcs_idx * step;
    value  = 3;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    /* cfg CpuMacCtlCfg */
    tbl_id = CpuMacCtlCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    step   = CpuMacCtlCfg_cfgPort1Map_f - CpuMacCtlCfg_cfgPort0Map_f;
    fld_id = CpuMacCtlCfg_cfgPort0Map_f + port_idx * step;
    value  = pcs_idx;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &ctl_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    /* cfg sgmac Rx/Tx*/
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, (sgmac_idx == 0) ? 1 : 0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, (sgmac_idx == 0) ? 1 : 0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiXauiMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiRXauiMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiQsgmiiMode_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg per Share Mii*/
    sal_memset(fld_info, 0xff, 10 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFXMode0_f,            0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    16);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    17);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      0x3fff);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxRsFecEn0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeedRx0_f,           10);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeed0_f,             9);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mii_idx, fld_num, fld_info));

    /* cfg SharedPcsCfg */
    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_cgMode_f,          0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_xlgMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_fxMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_lgMode0_f,         1);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_xxvgMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeRx0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeTx0_f,    0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));

#if 0
    /* shared_pcs_serdes_cfg */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, 80);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /*parallelizing check disable*/
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));
#endif
    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_cg_config(uint8 lchip, uint16 dport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint16 step                = 0;
    uint8  sgmac_idx           = 0;
    uint8  pcs_idx             = 0;
    uint8  core_id             = 0;
    uint8  port_idx            = 0;
    uint8  fld_num             = 0;
    reg_field_info_t fld_info[15]     = {{0}};
    sys_dmps_db_upt_info_t port_info  = {0};
    CpuMacCtlCfg_m             ctl_cfg;
    CpuMacClockTreeCfg_m       clk_tree_cfg;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,         pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,        port_idx);

    sgmac_idx  = pcs_idx;
    
    /* cfg CpuMacClockTreeCfg */
    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    step   = CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f - CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f - CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f - CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f;
    fld_id = CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f - CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f;
    fld_id = CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f + pcs_idx * step;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    fld_id = CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f;
    value  = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f - CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f;
    fld_id = CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f + pcs_idx * step;
    value  = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    step   = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f - CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f;
    fld_id = CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f + pcs_idx * step;
    value  = 3;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &clk_tree_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &clk_tree_cfg));

    /* cfg CpuMacCtlCfg */
    tbl_id = CpuMacCtlCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    step   = CpuMacCtlCfg_cfgPort1Map_f - CpuMacCtlCfg_cfgPort0Map_f;
    fld_id = CpuMacCtlCfg_cfgPort0Map_f + port_idx * step;
    value  = pcs_idx;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value, &ctl_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ctl_cfg));

    /* cfg sgmac Rx/Tx*/
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, 0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, 0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, sgmac_idx, fld_num, fld_info));

    /* cfg Share Mii*/
    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiXauiMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiRXauiMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiQsgmiiMode_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, 1);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_cfg(lchip, core_id, 0, fld_num, fld_info));

    /* cfg per Share Mii*/
    sal_memset(fld_info, 0xff, 10 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFXMode0_f,            0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    32);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      0x3fff);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxRsFecEn0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeedRx0_f,           10);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiSpeed0_f,             10);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /* cfg SharedPcsCfg */
    sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_cgMode_f,          1);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0,       SharedPcsCfg_xlgMode_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_fxMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_lgMode0_f,         0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_xxvgMode0_f,       0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeRx0_f,    0);
    SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_sgmiiModeTx0_f,    0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));

#if 0
    /* shared_pcs_serdes_cfg */
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, 80);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    /*parallelizing check disable*/
    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, 0);
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  0);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));
#endif
    return CTC_E_NONE;
}

/*Quad Group                     cfgQuadSgmacRxBufMode cfgQuadSgmacTxBufMode cfgSharedMiiMuxMode*/
/*1×40G/100G                     3'b010                3'b010                3'b010             */
/*2×50G                          3'b111                3'b111                3'b111             */
/*50G Port0 + 2*1G/10G/25G/none  3'b101                3'b101                3'b101             */
/*50G Port1 + 2*1G/10G/25G/none  3'b110                3'b110                3'b110             */
/*4×1G/10G/25G/none              3'b000                3'b000                3'b000             */
int32
_sys_at_cpumac_set_quad_group_mode(uint8 lchip, uint8 core_id, uint8 mac_idx, uint8 if_mode)
{
    uint32 cmd      = 0;
    uint8  is_lg0   = FALSE;
    uint8  is_lg1   = FALSE;
    uint8  is_quad  = FALSE;
    uint8  is_first_half = FALSE;
    uint32 mode_val0 = 0;
    uint32 mode_val1 = 0;
    uint32 mode_val2 = 0;
    QuadSgmacCfg_m mac_cfg;
    SharedMiiCfg_m mii_cfg;
#if 0
    /*get quad value*/
    is_quad = ((CTC_CHIP_SERDES_XLG_MODE == p_hss_vec->serdes_info[0].mode) || 
              (CTC_CHIP_SERDES_CG_MODE == p_hss_vec->serdes_info[0].mode)) ? TRUE : FALSE;
    is_lg0  = (CTC_CHIP_SERDES_LG_MODE == p_hss_vec->serdes_info[0].mode) ? TRUE : FALSE;
    is_lg1  = (CTC_CHIP_SERDES_LG_MODE == p_hss_vec->serdes_info[2].mode) ? TRUE : FALSE;
#endif

    /*get quad value*/
    is_quad = ((CTC_CHIP_SERDES_XLG_MODE == if_mode) || (CTC_CHIP_SERDES_CG_MODE == if_mode)) ? TRUE : FALSE;
    is_lg0  = ((CTC_CHIP_SERDES_LG_MODE == if_mode) && (0 == mac_idx)) ? TRUE : FALSE;
    is_lg1  = ((CTC_CHIP_SERDES_LG_MODE == if_mode) && (2 == mac_idx)) ? TRUE : FALSE;
    is_first_half = (2 > mac_idx) ? TRUE : FALSE;

    cmd = DRV_IOR(QuadSgmacCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_cfg));
    DRV_IOR_FIELD(lchip, QuadSgmacCfg_t, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &mode_val0, &mac_cfg);
    DRV_IOR_FIELD(lchip, QuadSgmacCfg_t, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &mode_val1, &mac_cfg);

    cmd = DRV_IOR(SharedMiiCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mii_cfg));
    DRV_IOR_FIELD(lchip, SharedMiiCfg_t, SharedMiiCfg_cfgSharedMiiMuxMode_f, &mode_val2, &mii_cfg);
    
    if(is_quad)
    {
        mode_val0 = 0x00000002; /*1*40G/100G*/
        mode_val1 = 0x00000002; /*1*40G/100G*/
        mode_val2 = 0x00000002; /*1*40G/100G*/
    }
    else
    {
        if(is_lg0)
        {
            mode_val0 |= 0x00000005; /*50G port0 + xxx*/
            mode_val1 |= 0x00000005; /*50G port0 + xxx*/
            mode_val2 |= 0x00000005; /*50G port0 + xxx*/
        }
        else if(is_lg1)
        {
            mode_val0 |= 0x00000006; /*xxx + 50G port2*/
            mode_val1 |= 0x00000006; /*xxx + 50G port2*/
            mode_val2 |= 0x00000006; /*xxx + 50G port2*/
        }
        else if(is_first_half)
        {
            mode_val0 &= 0xfffffffe; /*2*1G/10G/25G/none + xxx*/
            mode_val1 &= 0xfffffffe; /*2*1G/10G/25G/none + xxx*/
            mode_val2 &= 0xfffffffe; /*2*1G/10G/25G/none + xxx*/
        }
        else
        {
            mode_val0 &= 0xfffffffd; /*xxx + 2*1G/10G/25G/none*/
            mode_val1 &= 0xfffffffd; /*xxx + 2*1G/10G/25G/none*/
            mode_val2 &= 0xfffffffd; /*xxx + 2*1G/10G/25G/none*/
        }
    }

    /*QuadSgmacCfg.cfgQuadSgmacRxBufMode*/
    /*QuadSgmacCfg.cfgQuadSgmacTxBufMode*/
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, QuadSgmacCfg_t, 0, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &mode_val0, &mac_cfg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, QuadSgmacCfg_t, 0, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &mode_val1, &mac_cfg);
    cmd = DRV_IOW(QuadSgmacCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_cfg));

    /*SharedMiiCfg.cfgSharedMiiMuxMode*/
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SharedMiiCfg_t, 0, SharedMiiCfg_cfgSharedMiiMuxMode_f, &mode_val2, &mii_cfg);
    cmd = DRV_IOW(SharedMiiCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mii_cfg));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_mac_config(uint8 lchip, uint16 mac_id)
{
    uint8  core_id = SYS_AT_GET_CORE_BY_CPU_SERDES(mac_id);
    uint8  if_mode = 0;
    uint8  mac_idx = 0;
    uint16 dport   = 0;
    sys_dmps_db_upt_info_t port_info  = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);

    switch (if_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmii_config(lchip, dport));
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_xfi_config(lchip, dport));
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_xlg_config(lchip, dport));
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_xxvg_config(lchip, dport));
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_lg_config(lchip, dport));
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_cg_config(lchip, dport));
            break;
        default:
            break;
    }
    /*quad group public config*/
    CTC_ERROR_RETURN(_sys_at_cpumac_set_quad_group_mode(lchip, core_id, mac_idx, if_mode));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_fec_xfi_xlg_cfg(uint8 lchip, uint8 core_id, uint32 value, uint8 internal_mac_idx, uint8 if_mode, uint8 rx_flag)
{
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint32 step     = 0;
    uint8  port_cnt = 0;
    uint32 field_id_base = 0;
    ResetCtlSharedFec_m rst_fec;

    tbl_id = ResetCtlSharedFec_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rst_fec));

    step = ResetCtlSharedFec_cfgSoftRstFecRx1_f - ResetCtlSharedFec_cfgSoftRstFecRx0_f;
    field_id_base = rx_flag ? ResetCtlSharedFec_cfgSoftRstFecRx0_f : ResetCtlSharedFec_cfgSoftRstFecTx0_f;
    if(CTC_CHIP_SERDES_XFI_MODE == if_mode)
    {
        field_id = field_id_base + step*internal_mac_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &rst_fec);
    }
    else if(CTC_CHIP_SERDES_XLG_MODE == if_mode)
    {
        for(; port_cnt < 4; port_cnt++)
        {
            field_id = field_id_base + step*port_cnt;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &rst_fec);
        }
    }

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rst_fec));

    return CTC_E_NONE;
}

int32 
_sys_at_cpumac_set_hss_tx_reset(uint8 lchip, uint8 core_id, uint8 pcs_idx, uint8 lane_num, uint32 val_rst, uint8 swap_flag)
{
    uint8    idx         = 0;
    uint32   cmd         = 0;
    uint32   value[4]    = {0};
    fld_id_t field_id[4] = {0};
    CpuMacCtlResetCtl_m rst_ctl;

    if(lane_num > 4)
    {
        return CTC_E_INVALID_PARAM;
    }

    /*reset lane consider swap*/
    if(TRUE == swap_flag)
    {
        if (1 == lane_num)
        {
            switch (pcs_idx)
            {
            case 0:
                field_id[0] = CpuMacCtlResetCtl_resetHssTxLane2_f;
                break;
            case 1:
                field_id[0] = CpuMacCtlResetCtl_resetHssTxLane1_f;
                break;
            case 2:
                field_id[0] = CpuMacCtlResetCtl_resetHssTxLane0_f;
                break;
            case 3:
            default:    
                field_id[0] = CpuMacCtlResetCtl_resetHssTxLane3_f;
                break;
            }
            value[0] = val_rst;
        }
        else if(2 == lane_num)
        {
            switch (pcs_idx)
            {
            case 0:
                field_id[0] = CpuMacCtlResetCtl_resetHssTxLane2_f;
                field_id[1] = CpuMacCtlResetCtl_resetHssTxLane1_f;
                break;
            case 2:
            default:
                field_id[0] = CpuMacCtlResetCtl_resetHssTxLane0_f;
                field_id[1] = CpuMacCtlResetCtl_resetHssTxLane3_f;
                break;
            }
            value[0] = val_rst;
            value[1] = val_rst;
        }
        else if(4 == lane_num)
        {
            field_id[0] = CpuMacCtlResetCtl_resetHssTxLane2_f;
            field_id[1] = CpuMacCtlResetCtl_resetHssTxLane1_f;
            field_id[2] = CpuMacCtlResetCtl_resetHssTxLane0_f;
            field_id[3] = CpuMacCtlResetCtl_resetHssTxLane3_f;
            value[0] = val_rst;
            value[1] = val_rst;
            value[2] = val_rst;
            value[3] = val_rst;
        }
    }
    else
    {
        for(idx = 0; idx < lane_num; idx++)
        {
            field_id[idx] = CpuMacCtlResetCtl_resetHssTxLane0_f + idx + pcs_idx;
            value[idx] = val_rst;
        }
    }

    cmd = DRV_IOR(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rst_ctl));
    for(idx = 0; idx < lane_num; idx++)
    {
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, field_id[idx], &(value[idx]), &rst_ctl);
    }
    cmd = DRV_IOW(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rst_ctl));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_reset_sgmac_rx_buffer(uint8 lchip, uint16 dport, uint8 enable)
{
    uint8  core_id          = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = QuadSgmacReserved_t;
    uint32 value            = 0;
    uint8  internal_mac_idx = 0;
    sys_dmps_db_upt_info_t    port_info = {0};
    QuadSgmacReserved_m mac_rsv;

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      internal_mac_idx);

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rsv));
    DRV_IOR_FIELD(lchip, tbl_id, QuadSgmacReserved_reserved_f, &value, &mac_rsv);
    if(enable)
    {
        value |= (1 << internal_mac_idx);
    }
    else
    {
        value &= (~(1 << internal_mac_idx));
    }
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, QuadSgmacReserved_reserved_f, &value, &mac_rsv);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rsv));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_sgmii_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    if(en)  /* release reset */
    {
        value = 0;
        /* Release Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Release Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 1, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
    }
    else     /* Assert reset */
    {
        value = 1;

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 1, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_sgmii_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    if(en)  /* release reset */
    {
        /* Release Mii Rx Soft Reset */
        /* SGMII & 2.5G do not use monitor RX auto, so RX MII reset will be 0 immediately. */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Release Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));
    }
    else     /* Assert reset */
    {
        /* Assert Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 1));
        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 0));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_sgmii_en(uint8 lchip, uint16 dport, uint8 enable)
{
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    if (enable)  /* release reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_sgmii_tx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_sgmii_rx_en(lchip, dport, &port_info, enable));
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_sgmii_rx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_sgmii_tx_en(lchip, dport, &port_info, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xfi_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint32  fec_en          = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XFI_MODE, FALSE));
        }
        /* Release Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Release Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 1, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
    }
    else     /* Assert reset */
    {
        value = 1;
        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 1, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XFI_MODE, FALSE));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xfi_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        /* Release Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Release Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XFI_MODE, TRUE));
        }
    }
    else     /* Assert reset */
    {
        value = 1;
        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XFI_MODE, TRUE));
        }
        /* Assert Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 1));
        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 0));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xfi_en(uint8 lchip, uint16 dport, uint8 enable)
{
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    if (enable)  /* release reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xfi_tx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xfi_rx_en(lchip, dport, &port_info, enable));
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xfi_rx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xfi_tx_en(lchip, dport, &port_info, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xlg_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    if (mii_idx != 0)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"Port: %d is not xlg mode \n", dport);
        return CTC_E_INVALID_PARAM;
    }

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XLG_MODE, FALSE));
        }
        /* Release Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstXlgTx_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Release Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 4, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
    }
    else     /* Assert reset */
    {
        value = 1;
        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 4, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstXlgTx_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XLG_MODE, FALSE));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xlg_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[3] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    if (mii_idx != 0)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"Port: %d is not xlg mode \n", dport);
        return CTC_E_INVALID_PARAM;
    }

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        /* Release Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Release Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_rxDeskewSoftRst_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstXlgRx_f,    0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XLG_MODE, TRUE));
        }
    }
    else     /* Assert reset */
    {
        value = 1;
        if (fec_en)
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mii_idx, CTC_CHIP_SERDES_XLG_MODE, TRUE));
        }
        /* Assert Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_rxDeskewSoftRst_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstXlgRx_f,    1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 1));
        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 0));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xlg_en(uint8 lchip, uint16 dport, uint8 enable)
{
    sys_dmps_db_upt_info_t port_info = {0};
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    if (enable)  /* release reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xlg_tx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xlg_rx_en(lchip, dport, &port_info, enable));
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xlg_rx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xlg_tx_en(lchip, dport, &port_info, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xxvg_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        /* Rlease Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            /* Release Fec Tx Soft Reset */
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecTx0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }

        /* Release Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Release Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 1, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
    }
    else     /* Assert reset */
    {
        value = 1;
        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 1, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecTx0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xxvg_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        /* Release Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Release Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Rlease Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }
    else     /* Assert reset */
    {
        /* Assert Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }

        /* Assert Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 1));
        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 0));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_xxvg_en(uint8 lchip, uint16 dport, uint8 enable)
{
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    if (enable)  /* release reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xxvg_tx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xxvg_rx_en(lchip, dport, &port_info, enable));
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xxvg_rx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xxvg_tx_en(lchip, dport, &port_info, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_lg_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        /* Rlease Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            /* Release Fec Tx Soft Reset */
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecTx0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }

        /* Release Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Release Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 2, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
    }
    else     /* Assert reset */
    {
        value = 1;
        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 2, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecTx0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_lg_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  core_id          = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        /* Release Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Release Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedPcsSoftRst_softRstPcsRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Rlease Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }
    else     /* Assert reset */
    {
        /* Assert Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }

        /* Assert Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedPcsSoftRst_softRstPcsRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 1));
        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 0));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_lg_en(uint8 lchip, uint16 dport, uint8 enable)
{
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    if (enable)  /* release reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_lg_tx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_lg_rx_en(lchip, dport, &port_info, enable));
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_lg_rx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_lg_tx_en(lchip, dport, &port_info, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_cg_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        value = 0;
        /* Rlease Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            /* Release Fec Tx Soft Reset */
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecTx0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }

        /* Release Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Release Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 4, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
    }
    else     /* Assert reset */
    {
        value = 1;
        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + mii_idx;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_at_cpumac_set_hss_tx_reset(lchip, core_id, pcs_idx, 4, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Pcs Tx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsTx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, ResetCtlSharedFec_cfgSoftRstFecTx0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_cg_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  core_id          = 0;
    uint32 fec_en           = 0;
    uint8  fld_num          = 0;
    reg_field_info_t fld_info[1] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mii_idx = p_port_info->mac_idx;
    pcs_idx = p_port_info->pcs_idx;
    core_id = p_port_info->core;

    /* get fec en */
    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    if(en)  /* release reset */
    {
        /* Release Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* Release Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Rlease Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }
    else     /* Assert reset */
    {
        /* Assert Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }

        /* Assert Pcs Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsSoftRst_softRstPcsRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

        /* Assert Mii Rx Soft Reset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mii_idx, SharedMiiResetCfg_cfgSoftRstRx0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 1));
        CTC_ERROR_RETURN(_sys_at_cpumac_reset_sgmac_rx_buffer(lchip, dport, 0));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_sgmac_cg_en(uint8 lchip, uint16 dport, uint8 enable)
{
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    if (enable)  /* release reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_cg_tx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_cg_rx_en(lchip, dport, &port_info, enable));
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_cg_rx_en(lchip, dport, &port_info, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_cg_tx_en(lchip, dport, &port_info, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_tx_en(uint8 lchip, uint16 dport, uint8 enable)
{
    uint8 if_mode = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                   dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       if_mode);

    /* PCS/MII/Sgmac/FEC reset or release */
    if (1 != SDK_WORK_PLATFORM)
    {
        switch(if_mode)
        {
            case CTC_CHIP_SERDES_SGMII_MODE:
            case CTC_CHIP_SERDES_2DOT5G_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_sgmii_tx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_XFI_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xfi_tx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_XLG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xlg_tx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_XXVG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xxvg_tx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_lg_tx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_CG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_cg_tx_en(lchip, dport, &port_info, enable));
                break;
            default:
                break;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_rx_en(uint8 lchip, uint16 dport, uint8 enable)
{
    uint8 if_mode = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                   dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       if_mode);

    /* PCS/MII/Sgmac/FEC reset or release */
    if (1 != SDK_WORK_PLATFORM)
    {
        switch(if_mode)
        {
            case CTC_CHIP_SERDES_SGMII_MODE:
            case CTC_CHIP_SERDES_2DOT5G_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_sgmii_rx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_XFI_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xfi_rx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_XLG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xlg_rx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_XXVG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_xxvg_rx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_lg_rx_en(lchip, dport, &port_info, enable));
                break;
            case CTC_CHIP_SERDES_CG_MODE:
                CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmac_cg_rx_en(lchip, dport, &port_info, enable));
                break;
            default:
                break;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_mac_en(uint8 lchip, uint16 dport, uint8 enable)
{
    uint32 link_mode = 0;
    uint8  an_en     = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_AN_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_AN_EN,     an_en);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode_by_dport(lchip, dport, &link_mode));

    if (enable)  /* release reset */
    {    
        CTC_ERROR_RETURN(_sys_at_cpumac_set_tx_en(lchip, dport, enable));
        if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_set_rx_en(lchip, dport, enable));
        }
        else
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_pcs_rst(lchip, dport, DMPS_RX, 0));
        }
    }
    else     /* Assert reset */
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_tx_en(lchip, dport, enable));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_rx_en(lchip, dport, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_fec_clear(uint8 lchip, uint16 dport)
{
    uint8  i         = 0;
    uint8  list_size = 0;
    uint8  mii_idx   = 0;
    uint8  pcs_idx   = 0;
    uint8  core_id   = 0;
    uint8  mode      = CTC_CHIP_SERDES_NONE_MODE;
    uint32 cmd       = 0;
    uint32 index     = 0;
    sys_at_drv_ioctl_info_t* p_cfg_mapping = NULL;
    sys_dmps_db_upt_info_t port_info       = {0};
    SharedMii0Cfg_m    share_mii;
    SharedPcsFecCfg_m  share_pcs_fec;
    GlobalCtlSharedFec_m global_ctl;
    XgFec0CtlSharedFec_m xg_fec_ctl;
    sys_at_drv_ioctl_info_t xfi_xxvg_cfg_mapping[] = {
    /*tbl_id                          field_id                                 value     *ptr */
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    0,     &share_mii},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,            0x3fff,     &share_mii},  /*1*/
 
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                            0,     &share_pcs_fec},  /*2*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        0,     &share_pcs_fec},  /*3*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                    0,     &share_pcs_fec},  /*4*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                        0,     &share_pcs_fec},  /*5*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       0,     &share_pcs_fec},  /*6*/

    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,            0,     &global_ctl},  /*7*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            0,     &global_ctl},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,      0,     &global_ctl},  /*9*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,      0,     &global_ctl},  /*10*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x3fff,     &global_ctl},  /*11*/

    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                1,     &xg_fec_ctl}}; /*12*/

    sys_at_drv_ioctl_info_t lg_cfg_mapping[] = {
    /*tbl_id                          field_id                                 value     *ptr */
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    0,     &share_mii},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,            0x3fff,     &share_mii},  /*1*/

    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                            0,     &share_pcs_fec},  /*2*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        0,     &share_pcs_fec},  /*3*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                    0,     &share_pcs_fec},  /*4*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                        0,     &share_pcs_fec},  /*5*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       0,     &share_pcs_fec},  /*6*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn1_f,                       0,     &share_pcs_fec},  /*7*/

    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,            0,     &global_ctl},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            0,     &global_ctl},  /*9*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,      0,     &global_ctl},  /*10*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,      0,     &global_ctl},  /*11*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f,      0,     &global_ctl},  /*12*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x3fff,     &global_ctl},  /*13*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x3fff,     &global_ctl},  /*14*/

    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl},  /*15*/
    {XgFec1CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl},  /*16*/
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl},  /*17*/
    {XgFec3CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl}}; /*18*/

    sys_at_drv_ioctl_info_t xlg_cg_cfg_mapping[] = {
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     0,     &share_mii},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x3fff,     &share_mii},  /*1*/
    {SharedMii1Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     0,     &share_mii},  /*2*/
    {SharedMii1Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x3fff,     &share_mii},  /*3*/
    {SharedMii2Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     0,     &share_mii},  /*4*/
    {SharedMii2Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x3fff,     &share_mii},  /*5*/
    {SharedMii3Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     0,     &share_mii},  /*6*/
    {SharedMii3Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x3fff,     &share_mii},  /*7*/

    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                             0,     &share_pcs_fec},  /*8*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                         0,     &share_pcs_fec},  /*9*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                     0,     &share_pcs_fec},  /*10*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn1_f,                         0,     &share_pcs_fec},  /*11*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode1_f,                     0,     &share_pcs_fec},  /*12*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                         0,     &share_pcs_fec},  /*13*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                        0,     &share_pcs_fec},  /*14*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn1_f,                        0,     &share_pcs_fec},  /*15*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn2_f,                        0,     &share_pcs_fec},  /*16*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn3_f,                        0,     &share_pcs_fec},  /*17*/

    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,             0,     &global_ctl},  /*18*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,             0,     &global_ctl},  /*19*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,       0,     &global_ctl},  /*20*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort1_f,             0,     &global_ctl},  /*21*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f,       0,     &global_ctl},  /*22*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,       0,     &global_ctl},  /*23*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f,       0,     &global_ctl},  /*24*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort2RsMode_f,       0,     &global_ctl},  /*25*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort3RsMode_f,       0,     &global_ctl},  /*26*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec40GPort_f,              0,     &global_ctl},  /*27*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,   0x3fff,     &global_ctl},  /*28*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,   0x3fff,     &global_ctl},  /*29*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f,   0x3fff,     &global_ctl},  /*30*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval3_f,   0x3fff,     &global_ctl},  /*31*/

    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl},  /*32*/
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl},  /*33*/
    {XgFec3CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl},  /*34*/
    {XgFec6CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1,     &xg_fec_ctl}}; /*35*/

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d, fec none\n", dport);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                   dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,            mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,            pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       mode);

    if((CTC_CHIP_SERDES_XFI_MODE == mode) || (CTC_CHIP_SERDES_XXVG_MODE == mode))
    {
        p_cfg_mapping = xfi_xxvg_cfg_mapping;
        list_size = sizeof(xfi_xxvg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);
      
        p_cfg_mapping[0].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[1].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[3].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[4].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecRsMode1_f
                                - SharedPcsFecCfg_lgPcsFecRsMode0_f);
        p_cfg_mapping[6].fld_id += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[8].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);
        p_cfg_mapping[9].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f);
        p_cfg_mapping[10].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[11].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[12].tbl_id += (pcs_idx % 4 )* (XgFec2CtlSharedFec_t - XgFec0CtlSharedFec_t);
    }    
    else if(CTC_CHIP_SERDES_LG_MODE == mode)
    {
        p_cfg_mapping = lg_cfg_mapping;
        list_size = sizeof(lg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);
     
        p_cfg_mapping[0].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[1].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[3].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[4].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecRsMode1_f
                                - SharedPcsFecCfg_lgPcsFecRsMode0_f);
        p_cfg_mapping[6].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[7].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[9].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);
        p_cfg_mapping[10].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f);
        p_cfg_mapping[11].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec25GPort2RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[12].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec25GPort2RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[13].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[14].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[15].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[16].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[17].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[18].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
    }
    else if((CTC_CHIP_SERDES_XLG_MODE == mode) || (CTC_CHIP_SERDES_CG_MODE == mode))
    {
        p_cfg_mapping = xlg_cg_cfg_mapping;
        list_size = sizeof(xlg_cg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);
    }

    for(i = 0; i < list_size; i++)
    {
        cmd = DRV_IOR(p_cfg_mapping[i].tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_mapping[i].ptr));

        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, p_cfg_mapping[i].tbl_id, 0, p_cfg_mapping[i].fld_id, &(p_cfg_mapping[i].value), p_cfg_mapping[i].ptr);

        cmd = DRV_IOW(p_cfg_mapping[i].tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_mapping[i].ptr));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_fec_baser(uint8 lchip, uint16 dport, uint8 fec_val)
{
    uint8  i         = 0;
    uint8  list_size = 0;
    uint8  pcs_idx   = 0;
    uint8  core_id   = 0;
    uint32 cmd       = 0;
    uint32 index     = 0;
    uint8 mode       = CTC_CHIP_SERDES_NONE_MODE;
    sys_at_drv_ioctl_info_t* p_cfg_mapping = NULL;
    sys_dmps_db_upt_info_t port_info       = {0};
    SharedPcsFecCfg_m  share_pcs_fec;
    GlobalCtlSharedFec_m global_ctl;
    XgFec0CtlSharedFec_m xg_fec_ctl;
    ResetCtlSharedFec_m  rst_ctl;

    sys_at_drv_ioctl_info_t xfi_cfg_mapping[] = {
    /*tbl_id                field_id                                          value      *ptr */
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff,     &global_ctl},  /*0*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                        1,     &share_pcs_fec},   /*1*/
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*2*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*3*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*4*/ 

    sys_at_drv_ioctl_info_t xlg_cfg_mapping[] = {
    /*tbl_id                field_id                                           value      *ptr */
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff,     &global_ctl},  /*0*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x13fff,     &global_ctl},  /*1*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f,  0x13fff,     &global_ctl},  /*2*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval3_f,  0x13fff,     &global_ctl},  /*3*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                         0,     &share_pcs_fec},  /*4*/ 
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*5*/ 
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*6*/ 
    {XgFec4CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*7*/ 
    {XgFec6CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*8*/ 
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec40GPort_f,              1,     &global_ctl},  /*9*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*10*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*11*/

    sys_at_drv_ioctl_info_t xxvg_cfg_mapping[] = {
    /*tbl_id                field_id                                            value     *ptr */
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff,     &global_ctl},  /*0*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                        1,     &share_pcs_fec},   /*1*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,       0,     &global_ctl},  /*2*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*3*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*4*/

    sys_at_drv_ioctl_info_t lg_cfg_mapping[] = {
    /*tbl_id                field_id                                            value     *ptr */   
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff,     &global_ctl},  /*0*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x13fff,     &global_ctl},  /*1*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                         1,     &share_pcs_fec},   /*2*/                
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,             1,     &global_ctl},   /*3*/
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*4*/ 
    {XgFec1CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*5*/ 
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*6*/ 
    {XgFec3CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0,     &xg_fec_ctl},  /*7*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*8*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*9*/

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport: %d, fec: %d\n", dport, fec_val);

    
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                   dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,            pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       mode);

    if(CTC_CHIP_SERDES_XFI_MODE == mode)
    {
        p_cfg_mapping = xfi_cfg_mapping;
        list_size = sizeof(xfi_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);

        p_cfg_mapping[0].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[1].fld_id += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[2].tbl_id += (pcs_idx % 4) * (XgFec2CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[3].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecRx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecRx0_f);
        p_cfg_mapping[4].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecTx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecTx0_f);
    }
    else if(CTC_CHIP_SERDES_XXVG_MODE == mode)
    {
        p_cfg_mapping = xxvg_cfg_mapping;
        list_size = sizeof(xxvg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);

        p_cfg_mapping[0].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[1].fld_id += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[2].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[3].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecRx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecRx0_f);
        p_cfg_mapping[4].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecTx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecTx0_f);
    }
    else if(CTC_CHIP_SERDES_XLG_MODE == mode)
    {
        p_cfg_mapping = xlg_cfg_mapping;
        list_size = sizeof(xlg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);
    }
    else if(CTC_CHIP_SERDES_LG_MODE == mode)
    {
        p_cfg_mapping = lg_cfg_mapping;
        list_size = sizeof(lg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);

        p_cfg_mapping[0].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[1].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[2].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[3].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);

        p_cfg_mapping[4].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[5].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[6].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[7].tbl_id += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);

        p_cfg_mapping[8].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecRx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecRx0_f);
        p_cfg_mapping[9].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecTx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecTx0_f);
    }
    
    for(i = 0; i < list_size; i++)
    {
        cmd = DRV_IOR(p_cfg_mapping[i].tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_mapping[i].ptr));

        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, p_cfg_mapping[i].tbl_id, 0, p_cfg_mapping[i].fld_id, &(p_cfg_mapping[i].value), p_cfg_mapping[i].ptr);

        cmd = DRV_IOW(p_cfg_mapping[i].tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_mapping[i].ptr));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_fec_rs(uint8 lchip, uint16 dport, uint8 fec_val)
{   
    uint8  i         = 0;
    uint8  list_size = 0;
    uint8  pcs_idx   = 0;
    uint8  mii_idx   = 0;
    uint8  core_id   = 0;
    uint8  mode      = CTC_CHIP_SERDES_NONE_MODE;
    uint32 cmd       = 0;
    uint32 index     = 0;
    sys_at_drv_ioctl_info_t* p_cfg_mapping = NULL;
    sys_dmps_db_upt_info_t port_info       = {0};
    SharedMii0Cfg_m    share_mii;
    SharedPcsFecCfg_m  share_pcs_fec;
    GlobalCtlSharedFec_m global_ctl;
    ResetCtlSharedFec_m  rst_ctl;

    sys_at_drv_ioctl_info_t xxlg_cfg_mapping[] = {
    /*tbl_id                field_id                                          value      *ptr */
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    1,     &share_mii},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,            0x4fff,     &share_mii},  /*1*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       1,     &share_pcs_fec},  /*2*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,       1,    &global_ctl},  /*3*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff,    &global_ctl},  /*4*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*5*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*6*/ 

    sys_at_drv_ioctl_info_t lg_cfg_mapping[] = {
    /*tbl_id                field_id                                           value     *ptr */
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    1,     &share_mii},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,            0x4fff,     &share_mii},  /*1*/

    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        1,     &share_pcs_fec},  /*2*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                    1,     &share_pcs_fec},  /*3*/     
    
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x9fff,     &global_ctl},  /*4*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x9fff,     &global_ctl},  /*5*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            1,     &global_ctl},  /*6*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,      1,     &global_ctl},  /*7*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*8*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*9*/ 

    sys_at_drv_ioctl_info_t cg_cfg_mapping[] = {
    /*tbl_id                field_id                                           value     *ptr */
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    1,     &share_mii},  /*0*/
    {SharedMii1Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    1,     &share_mii},  /*1*/
    {SharedMii2Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    1,     &share_mii},  /*2*/
    {SharedMii3Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                    1,     &share_mii},  /*3*/
        
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                            1,     &share_pcs_fec},  /*4*/

    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff,     &global_ctl},  /*5*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x13fff,     &global_ctl},  /*6*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f,  0x13fff,     &global_ctl},  /*7*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval3_f,  0x13fff,     &global_ctl},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,             1,     &global_ctl},  /*9*/

    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecRx0_f,                  0,     &rst_ctl},     /*10*/
    {ResetCtlSharedFec_t,   ResetCtlSharedFec_cfgSoftRstFecTx0_f,                  0,     &rst_ctl}};    /*11*/ 

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport: %d, fec: %d\n", dport, fec_val);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                   dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,            mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,            pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       mode);

    if(CTC_CHIP_SERDES_XXVG_MODE == mode)
    {
        p_cfg_mapping = xxlg_cfg_mapping;
        list_size = sizeof(xxlg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);

        p_cfg_mapping[0].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[1].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[2].fld_id += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[3].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[4].fld_id += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[5].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecRx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecRx0_f);
        p_cfg_mapping[6].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecTx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecTx0_f);
    }
    else if(CTC_CHIP_SERDES_LG_MODE == mode)
    {
        p_cfg_mapping = lg_cfg_mapping;
        list_size = sizeof(lg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);

        p_cfg_mapping[0].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[1].tbl_id  = (3 == mii_idx) ? SharedMii3Cfg_t : (SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t));
        p_cfg_mapping[2].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[3].fld_id += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecRsMode1_f
                                - SharedPcsFecCfg_lgPcsFecRsMode0_f);
        p_cfg_mapping[4].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[5].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f
                                - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[6].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);
        p_cfg_mapping[7].fld_id += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f
                                - GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f);
        p_cfg_mapping[8].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecRx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecRx0_f);
        p_cfg_mapping[9].fld_id += (pcs_idx % 4) * (ResetCtlSharedFec_cfgSoftRstFecTx1_f
                                - ResetCtlSharedFec_cfgSoftRstFecTx0_f);
    }
    else if(CTC_CHIP_SERDES_CG_MODE == mode)
    {
        p_cfg_mapping = cg_cfg_mapping;
        list_size = sizeof(cg_cfg_mapping) / sizeof(sys_at_drv_ioctl_info_t);
    }

    for(i = 0; i < list_size; i++)
    {
        cmd = DRV_IOR(p_cfg_mapping[i].tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_mapping[i].ptr));

        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, p_cfg_mapping[i].tbl_id, 0, p_cfg_mapping[i].fld_id, &(p_cfg_mapping[i].value), p_cfg_mapping[i].ptr);

        cmd = DRV_IOW(p_cfg_mapping[i].tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_mapping[i].ptr));
    }

    return CTC_E_NONE;

}

int32
_sys_at_cpumac_set_fec_config(uint8 lchip, uint16 dport, uint8 fec_val)
{
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d, fec val : %d\n", dport, fec_val);

    /*param check moved outside before mac dis*/

    /*FEC Configure*/
    if(SYS_DMPS_FEC_TYPE_NONE == fec_val)
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_clear(lchip, dport));
        return CTC_E_NONE;
    }

    switch(fec_val)
    {
        case SYS_DMPS_FEC_TYPE_RS528:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_clear(lchip, dport));
            CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_rs(lchip, dport, fec_val));
            break;
        case SYS_DMPS_FEC_TYPE_FC2112:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_clear(lchip, dport));
            CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_baser(lchip, dport, fec_val));
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_mcmac_pre_config(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  mac_idx = 0;
    uint8  fld_num = 0;
    reg_field_info_t fld_info[2] = {{0}};
    
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 0, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 1, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 2, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 3, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 0, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 1, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 2, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 3, HssLaneCfg_cfgPmaReady4PcsMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 0, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 1, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 2, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 0, 3, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 0, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 1, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 2, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));
    CTC_ERROR_RETURN(_sys_at_mac_set_hss_lane_cfg_reg(lchip, core_id, mac_group_id, 1, 3, HssLaneCfg_cfgPmaReady4AnethMaskLane, 0x3d));

    for (mac_idx = 0; mac_idx < AT_MAC_ID_NUM_PER_MCMAC; mac_idx++)
    {
        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMacRxSoftReset_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMiiRxSoftReset_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacTxSoftReset_cfgMcMacMacTxSoftReset_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultMaskLinkEn_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkDownForceFault_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        if (g_at_hata_en)
        {
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataSoftResetCfg_cfgMcHataTxSoftReset_f, 1);
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataSoftResetCfg_cfgMcHataRxSoftReset_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataEnable_cfgHataRxEnable_f, 1);
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataEnable_cfgHataTxEnable_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_enable(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_init_mac_pre_config(uint8 lchip, uint8 core_id)
{
    uint8  idx     = 0;
    uint8  fld_num = 0;
    uint32 value   = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    reg_field_info_t fld_info[2] = {{0}};
    CpuMacHssLaneCfg_m cpumac_lane_cfg;

    /* SharedMii0...3Cfg_cfgMiiFaultMaskLinkEn0 */
    for (idx = 0; idx < SYS_AT_CPUMAC_SERDES_NUM; idx++)
    {
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, idx, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        SET_REG_SOURCE_FIELD_INFO(fld_info, idx, SharedMii0Cfg_cfgMiiRxPCHLen0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, idx, 1, fld_info));
        value = fld_info[0].value;
        value |= 0x00000001;
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxPCHLen0_f, value);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, idx, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, idx, fld_num, fld_info));
   }

    index  = DRV_INS(0, 0);
    cmd    = DRV_IOR(CpuMacHssLaneCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_lane_cfg));
    value  = 0x3d;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgPmaReady4PcsMaskLane0_f, &value, &cpumac_lane_cfg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgPmaReady4PcsMaskLane1_f, &value, &cpumac_lane_cfg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgPmaReady4AnethMaskLane0_f, &value, &cpumac_lane_cfg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgPmaReady4AnethMaskLane1_f, &value, &cpumac_lane_cfg);

    cmd    = DRV_IOW(CpuMacHssLaneCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_lane_cfg));
    
    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_group_enable(uint8 lchip, uint8 core_id, uint8 enable)
{
    uint32 value   = 0;
    uint32 cmd     = 0;
    uint32 index   = DRV_INS(0, 0);
    uint8  fld_num = 0;
    reg_field_info_t fld_info[2] = {{0}};
    CpuMacCtlEnClk_m      cm_en;
    CpuMacCtlResetCtl_m   cpumac_ctl_reset;
    QuadSgmacInitDone_m   quad_sgmac_init_done;

    if (enable)
    {
        /* Enable CpuMac clock */
        cmd = DRV_IOR(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cm_en));
        value = 1;
        //DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkLed_f, &value, &cm_en);
        //DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkQuadSgmac_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac0_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac1_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac2_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac3_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs0_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs1_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs2_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs3_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs0_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs1_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs2_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs3_f, &value, &cm_en);
        cmd = DRV_IOW(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cm_en));

        /* Release CpuMacCtlReset */
        cmd = DRV_IOR(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_ctl_reset));
        value = 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii0_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii1_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii2_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii3_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs0_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs1_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs2_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs3_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac0_f, &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac1_f, &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac2_f, &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac3_f, &value, &cpumac_ctl_reset);
        cmd = DRV_IOW(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_ctl_reset));

        /* QuadSgmacInit */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, QuadSgmacInit_init_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_quad_sgmac_init(lchip, core_id, 0, fld_num, fld_info));

        /* QuadSgmacStatsCfg */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, QuadSgmacStatsCfg_maxInitCnt_f, 159);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_quad_sgmac_stats_cfg(lchip, core_id, 0, fld_num, fld_info));

        /* QuadSgmacInit */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, QuadSgmacInit_init_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_quad_sgmac_init(lchip, core_id, 0, fld_num, fld_info));

#ifdef EMULATION_ENV
        sal_task_sleep(200);
#else
        sal_task_sleep(1);
#endif

        /* Wait QuadSgmacInitDone */
        cmd    = DRV_IOR(QuadSgmacInitDone_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &quad_sgmac_init_done));
        DRV_IOR_FIELD(lchip, QuadSgmacInitDone_t, QuadSgmacInitDone_initDone_f, &value, &quad_sgmac_init_done);
        if (0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QuadSgmacInit] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
    }
    else
    {
        /* CpuMacCtlReset */
        cmd = DRV_IOR(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_ctl_reset));
        value = 1;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii0_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii1_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii2_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii3_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs0_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs1_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs2_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs3_f,   &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac0_f, &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac1_f, &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac2_f, &value, &cpumac_ctl_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac3_f, &value, &cpumac_ctl_reset);
        cmd = DRV_IOW(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_ctl_reset));

        /* Close CpuMac clock */
        cmd = DRV_IOR(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cm_en));
        value = 0;
        //DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkLed_f, &value, &cm_en);
        //DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkQuadSgmac_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac0_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac1_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac2_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac3_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs0_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs1_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs2_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs3_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs0_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs1_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs2_f, &value, &cm_en);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs3_f, &value, &cm_en);
        cmd = DRV_IOW(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cm_en));
    }

    return CTC_E_NONE;
}

uint8
_sys_at_cpumac_is_power_up(uint8 lchip, uint8 core_id)
{
    uint8  cpumac_idx     = 0;
    uint16 psd            = 0;
    uint32 serdes_speed   = 0;

    for (cpumac_idx = 0; cpumac_idx < AT_CPUMAC_PER_CORE; cpumac_idx++)
    {
        psd = DMPS_MAX_SERDES_NUM_PER_CORE * DMPS_MAX_CORE_NUM + core_id * AT_CPUMAC_PER_CORE + cpumac_idx;
        (void) sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed);
        if (serdes_speed)
        {
            return TRUE;
        }
    }

    return FALSE;
}

int32
_sys_at_cpumac_init_mac_config(uint8 lchip, uint8 core_id)
{
    uint8  cpumac_idx = 0;
    uint16 mac_id     = 0;

    CTC_ERROR_RETURN(_sys_at_cpumac_init_mac_pre_config(lchip, core_id));

    /*CPUMAC initial config*/
    for(cpumac_idx = 0; cpumac_idx < AT_CPUMAC_PER_CORE; cpumac_idx++)
    {
        mac_id = DMPS_MAX_MAC_NUM_PER_CORE * DMPS_MAX_CORE_NUM + core_id * AT_CPUMAC_PER_CORE + cpumac_idx;
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_MAC, mac_id));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_mac_config(lchip, mac_id));
        CTC_ERROR_RETURN(_sys_at_mac_init_cl73_ability(lchip, core_id, mac_id));
    }

    if (!_sys_at_cpumac_is_power_up(lchip, core_id))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_group_enable(lchip, core_id, FALSE));
    }

    return CTC_E_NONE;
}

#ifdef EMULATION_ENV
uint32
_sys_at_mac_get_lcm_walkend(uint8 lchip, uint8* speed_num, uint8* lcm_walkend)
{
    uint8 cnt = 0;
    uint8 walkend[8] = {80, 32, 20, 16, 8, 4, 2, 1}; /*0:10G,1:25G,2:40G,3:50G,4:100G,5:200G,6:400G,7:800G*/

    if (0 != speed_num[0]) /* 10G */
    {
        if (0 != speed_num[1]) /* 25G */
        {
            *lcm_walkend = 160;
        }
        else
        {
            *lcm_walkend = 80;
        }
    }
    else if (0 != speed_num[2]) /* 40G */
    {
        if (0 != speed_num[1]) /* 25G */
        {
            *lcm_walkend = 160;
        }
        else if (0 != speed_num[3]) /* 50G */
        {
            *lcm_walkend = 80;
        }
        else if (0 != speed_num[4]) /* 100G */
        {
            *lcm_walkend = 40;
        }
        else
        {
            *lcm_walkend = 20;
        }
    }
    else
    {
        for (cnt = 0; cnt < 8; cnt++)
        {
            if (0 != speed_num[cnt])
            {
                *lcm_walkend = walkend[cnt];
                return CTC_E_NONE;
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_macshim_cal(uint8 lchip, uint8 port_num, uint8 lcm_walkend,
                                uint8* walkend, uint8* port_idx, uint8* cfg_val)
{
    uint8 i = 0;
    uint8 j = 0;
    uint8 cnt = 0;
    uint8 temp = 0;
    uint8 cfg_num = 0;
    uint8 cfg_done = 0;
    uint8 entry = 0;

    /* sort */
    for (i = 0; i < port_num - 1; i++)
    {
        for (j = i + 1; j < port_num; j++)
        {
            if (walkend[i] > walkend[j])
            {
                temp       = walkend[i];
                walkend[i] = walkend[j];
                walkend[j] = temp;

                temp        = port_idx[i];
                port_idx[i] = port_idx[j];
                port_idx[j] = temp;
            }
        }
    }

    for (cnt = 0; cnt < lcm_walkend; cnt++)
    {
        cfg_val[cnt] = 0xff;
    }

    for (cnt = 0; cnt < port_num; cnt++)
    {
        cfg_num = lcm_walkend / walkend[cnt];
        cfg_done = 0;
        entry = 0;
        while (entry < lcm_walkend)

        {
            if ( 0xff != cfg_val[entry])
            {
                entry++;
                continue;
            }
            cfg_val[entry] = port_idx[cnt];
            cfg_done++;
            if (cfg_num == cfg_done)
            {
                break;
            }
            entry += walkend[cnt];
        }
        if (cfg_num > cfg_done)
        {
            sal_printf("MacShim Calendar is error. \n");
            return CTC_E_INVALID_PARAM;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_macshim_pre_group(uint8 lchip, uint8 mac_group_id)
{
#ifdef EMULATOR_ENV
    return CTC_E_NONE;
#endif
    uint8 cnt      = 0;
    uint8 port_num = 0;
    uint8 lane_num = 0;
    uint8 lane_idx = 0;
    uint8 shim_id  = 0;
    uint8 if_mode  = 0;
    uint8 speed_mode  = 0;
    uint8 lcm_walkend = 0;
    uint16 mac_id = 0;
    uint16 dport  = 0;
    uint16 chan_id = 0;
    uint16 speed  = 0;
    uint32 tbl_id = 0;
    uint32 cmd    = 0;
    uint32 value  = 0;
    uint32 fld_id = 0;
    uint32 index  = 0;
    uint32 serdes_speed = 0;
    uint32 cal_sel = 0;
    uint8 speed_num[8] = {0}; /*0:10G,1:25G,2:40G,3:50G,4:100G,5:200G,6:400G,7:800G*/
    uint8 port_idx[8] = {0};
    uint8 walkend[8] = {0};
    sys_dmps_db_upt_info_t port_info  = {0};
    uint8 cfg_val[160] = {0};
    uint8 shim_map[22] = {0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4};
    uint32 vlan[6][8] = {  /*10g    25g    40g    50g    100g   200g   400g   800g*/
                            {0x0  , 0x40 , 0x80 , 0xc0 , 0x100, 0x140, 0x180, 0x1c0},
                            {0x200, 0x240, 0x280, 0x2c0, 0x300, 0x340, 0x380, 0x3c0},
                            {0x400, 0x440, 0x480, 0x4c0, 0x500, 0x540, 0x580, 0x5c0},
                            {0x600, 0x640, 0x680, 0x6c0, 0x700, 0x740, 0x780, 0x7c0},
                            {0x800, 0x840, 0x880, 0x8c0, 0x900, 0x940, 0x980, 0x9c0},
                            {0xa00, 0xa40, 0xa80, 0xac0, 0xb00, 0xb40, 0xb80, 0xbc0}};
    int32 ret = CTC_E_NONE;
    MacShimRegCfg_m macshim_reg_cfg;
    MacShimRxRdCalendar_m macshim_rx_rd_cal;
    MacShimCalRxCtl_m macshim_cal_rx_ctl;
    MacShimCalRx_m macshim_cal_rx;
    MacShimCalRxBak_m macshim_cal_rx_bak;

    shim_id = (mac_group_id < 10) ? mac_group_id : (mac_group_id + 2);

    /* 1. cfg MacShimRegCfg */
    index  = DRV_INS(shim_id, 0);
    tbl_id = MacShimRegCfg_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_reg_cfg));
    value  = 1;
    fld_id = MacShimRegCfg_initCal_f;
    DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_reg_cfg));

    /* 2. cfg MacShimRxRdCalendar */
    tbl_id = MacShimRxRdCalendar_t;
    for (cnt = 0; cnt < 16; cnt++)
    {
        index  = DRV_INS(shim_id, cnt);
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_rx_rd_cal));
        value  = cnt;
        fld_id = MacShimRxRdCalendar_portId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_rx_rd_cal);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_rx_rd_cal));
    }

    /* 3. cfg MacShimRegCfg */
    index  = DRV_INS(shim_id, 0);
    tbl_id = MacShimRegCfg_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_reg_cfg));
    for (cnt = 0; cnt < AT_MAC_ID_NUM_PER_MCMAC; cnt++)
    {
        mac_id = cnt + mac_group_id * AT_MAC_ID_NUM_PER_MCMAC;
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES,   mac_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,  serdes_speed);
        SYS_CONDITION_CONTINUE(0 == serdes_speed);
        ret = sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_MAC, mac_id, DMPS_DB_TYPE_PORT, NULL, &dport);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != ret);
        ret = sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != ret);

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,   dport);
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,     if_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,  speed_mode);

        SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, lane_num);

        SYS_AT_SPEED_MODE_TO_SPEED_MODE(speed_mode, value);
        for (lane_idx = 0 ; lane_idx < lane_num; lane_idx++)
        {
            fld_id = MacShimRegCfg_port0SpeedMode_f + cnt + lane_idx;
            DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        }
        if (CTC_CHIP_SERDES_NONE_MODE == if_mode)
        {
            continue;
        }

        port_idx[port_num] = cnt;
        SYS_AT_SPEED_MODE_TO_SPEED_VALUE(speed_mode, speed);
        walkend[port_num] = 800 / speed;
        switch (speed)
        {
            case 10:
                speed_num[0]++;
                break;
            case 25:
                speed_num[1]++;
                break;
            case 40:
                speed_num[2]++;
                break;
            case 50:
                speed_num[3]++;
                break;
            case 100:
                speed_num[4]++;
                break;
            case 200:
                speed_num[5]++;
                break;
            case 400:
                speed_num[6]++;
                break;
            case 800:
                speed_num[7]++;
                break;
            default:
                break;
        }
        port_num++;
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_reg_cfg));

    /* 4. cfg MacShimCalRxCtl */
    _sys_at_mac_get_lcm_walkend(lchip, speed_num, &lcm_walkend);

    index  = DRV_INS(shim_id, 0);
    tbl_id = MacShimCalRxCtl_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_ctl));
    fld_id = MacShimCalRxCtl_calEntrySel_f;
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &cal_sel, &macshim_cal_rx_ctl);
    value  = lcm_walkend - 1;
    if (1 == cal_sel)
    {
        fld_id = MacShimCalRxCtl_cfgWalkerEnd_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_cal_rx_ctl);
    }
    else
    {
        fld_id = MacShimCalRxCtl_cfgWalkerEndBak_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_cal_rx_ctl);
    }
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_ctl));

    /* 5. cfg MacShimCalRx and MacShimCalRxBak */
    _sys_at_mac_get_macshim_cal(lchip, port_num, lcm_walkend, walkend, port_idx, cfg_val);

    if (1 == cal_sel)
    {
        for (cnt = 0; cnt < lcm_walkend; cnt++)
        {
            index  = DRV_INS(shim_id, cnt);
            tbl_id = MacShimCalRx_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx));
            value  = cfg_val[cnt];
            fld_id = MacShimCalRx_calEntry_f;
            DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_cal_rx);
            cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx));
        }
    }
    else
    {
        for (cnt = 0; cnt < lcm_walkend; cnt++)
        {
            index  = DRV_INS(shim_id, cnt);
            tbl_id = MacShimCalRxBak_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_bak));
            value  = cfg_val[cnt];
            fld_id = MacShimCalRxBak_calEntry_f;
            DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_cal_rx_bak);
            cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_bak));
        }
    }

    index  = DRV_INS(shim_id, 0);
    tbl_id = MacShimCalRxCtl_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_ctl));
    value  = (1 == cal_sel) ? 0 : 1;
    fld_id = MacShimCalRxCtl_calEntrySel_f;
    DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_cal_rx_ctl);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_ctl));

    /* 6. cfg MacShimCalRxCtl */
    index  = DRV_INS(shim_id, 0);
    tbl_id = MacShimCalRxCtl_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_ctl));
    value  = 1;
    fld_id = MacShimCalRxCtl_macShimCalRxReady_f;
    DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_cal_rx_ctl);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_cal_rx_ctl));

    if (0 != mac_group_id)
    {
        /* 6. cfg MacShimRegCfg */
        index  = DRV_INS(shim_id, 0);
        tbl_id = MacShimRegCfg_t;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_reg_cfg));
        //value  = 512;
        value = vlan[shim_map[shim_id]][0];
        fld_id = MacShimRegCfg_base10gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 576;
        value = vlan[shim_map[shim_id]][1];
        fld_id = MacShimRegCfg_base25gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 640;
        value = vlan[shim_map[shim_id]][2];
        fld_id = MacShimRegCfg_base40gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 704;
        value = vlan[shim_map[shim_id]][3];
        fld_id = MacShimRegCfg_base50gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 768;
        value = vlan[shim_map[shim_id]][4];
        fld_id = MacShimRegCfg_base100gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 832;
        value = vlan[shim_map[shim_id]][5];
        fld_id = MacShimRegCfg_base200gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 896;
        value = vlan[shim_map[shim_id]][6];
        fld_id = MacShimRegCfg_base400gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        //value  = 960;
        value = vlan[shim_map[shim_id]][7];
        fld_id = MacShimRegCfg_base800gVlanId_f;
        DRV_IOW_FIELD_NZ(0, 0xff, 0xff, lchip, tbl_id, shim_id, fld_id, &value, &macshim_reg_cfg);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, 0, cmd, &macshim_reg_cfg));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_macshim_config(uint8 lchip)
{
    CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, 0));
    CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, 1));

    return CTC_E_NONE;
}
#endif

int32
_sys_at_mcmac_set_group_enable(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 enable)
{
#if 0
    uint8  fld_num = 0;
    uint32 value   = 0;
    uint32 cmd     = 0;
    uint32 index   = DRV_INS(mac_group_id, 0);
    reg_field_info_t fld_info[26] = {{0}};
    CtcMacCtlEnClk_m     ctc_mac_ctl_enclk;
    CtcMacCtlReset_m     ctc_mac_ctl_rst;
    McMacInitDone_m      mac_init_done;
    McMacStatsInitDone_m mac_stats_init_done;

    if (enable)
    {
        /* Open clock enable:CtcMacCtlEnClk */
        cmd = DRV_IOR(CtcMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_enclk));
        value = 1;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkUart_f,    &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcuIntf_f, &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcu_f,     &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcMac_f,   &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcHata_f,  &value, &ctc_mac_ctl_enclk);
        cmd = DRV_IOW(CtcMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_enclk));

        /* Rlease Reset: CtcMacCtlReset */
        cmd = DRV_IOR(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));
        value = 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcPcs800_f, &value, &ctc_mac_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcMac_f,    &value, &ctc_mac_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcHata_f,   &value, &ctc_mac_ctl_rst);
        cmd = DRV_IOW(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));

        /* Open clock Enable:McPcs800EnClk */
        sal_memset(fld_info, 0xff, 7 * sizeof(reg_field_info_t));
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs800_f,      1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs400Core1_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs400Core0_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcFecCore1_f,    1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800EnClk_enClkMcFecCore1_f,    1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcFecCore0_f,    1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800EnClk_enClkMcFecCore0_f,    1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_en_clk(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* Init */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacInit_init_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_init(lchip, core_id, mac_group_id, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacStatsInit_quadSgmac0Init_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacStatsInit_quadSgmac1Init_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_stats_init(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* McMacStatsCfg */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacStats0Cfg_cfgMaxInitCnt0_f, 159);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_stats0_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacStats1Cfg_cfgMaxInitCnt1_f, 159);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_stats1_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* Init */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacInit_init_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_init(lchip, core_id, mac_group_id, fld_num, fld_info));

        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacStatsInit_quadSgmac0Init_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McMacStatsInit_quadSgmac1Init_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_stats_init(lchip, core_id, mac_group_id, fld_num, fld_info));

#ifdef EMULATION_ENV
        sal_task_sleep(200);
#else
        sal_task_sleep(1);
#endif

        /* Wait InitDone */
        cmd    = DRV_IOR(McMacInitDone_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_init_done));
        DRV_IOR_FIELD(lchip, McMacInitDone_t, McMacInitDone_initDone_f, &value, &mac_init_done);
        if (0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McMacInit.%d] Feature not initialized \n", mac_group_id);
            return CTC_E_NOT_INIT;
        }

        cmd    = DRV_IOR(McMacStatsInitDone_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats_init_done));
        DRV_IOR_FIELD(lchip, McMacStatsInitDone_t, McMacStatsInitDone_quadSgmac0InitDone_f, &value, &mac_stats_init_done);
        if (0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McMacStatsInit0.%d] Feature not initialized \n", mac_group_id);
            return CTC_E_NOT_INIT;
        }

        cmd    = DRV_IOR(McMacStatsInitDone_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats_init_done));
        DRV_IOR_FIELD(lchip, McMacStatsInitDone_t, McMacStatsInitDone_quadSgmac1InitDone_f, &value, &mac_stats_init_done);
        if (0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McMacStatsInit1.%d] Feature not initialized \n", mac_group_id);
            return CTC_E_NOT_INIT;
        }

        /* Rlease Reset: McPcs800Reset */
        sal_memset(fld_info, 0xff, 26 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcFec0_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcFec1_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcFecRx0_f,  0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcFecRx1_f,  0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcFecTx0_f,  0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcFecTx1_f,  0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcPcs0_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcPcs1_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcPcsReg0_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetMcPcsReg1_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 2, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 3, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 4, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 5, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 6, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 7, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 2, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 3, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 4, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 5, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 6, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        SET_REG_FIELD_INFO(fld_info, fld_num, 7, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* Mac/Pcs/Hata Pre Config */
        CTC_ERROR_RETURN(_sys_at_mac_pcs_pre_cfg(lchip, core_id, mac_group_id));
    }
    else
    {
        /* Close clock Enable:McPcs800EnClk */
        sal_memset(fld_info, 0xff, 7 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs800_f,      0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs400Core1_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcPcs400Core0_f, 0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcFecCore1_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800EnClk_enClkMcFecCore1_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800EnClk_enClkMcFecCore0_f,    0);
        SET_REG_FIELD_INFO(fld_info, fld_num, 1, McPcs800EnClk_enClkMcFecCore0_f,    0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_en_clk(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* Reset: CtcMacCtlReset */
        cmd = DRV_IOR(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));
        value = 1;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcPcs800_f, &value, &ctc_mac_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcMac_f,    &value, &ctc_mac_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcHata_f,   &value, &ctc_mac_ctl_rst);
        cmd = DRV_IOW(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));

        /* Close clock Enable:CtcMacCtlEnClk */
        cmd = DRV_IOR(CtcMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_enclk));
        value = 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkUart_f,    &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcuIntf_f, &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcu_f,     &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcMac_f,   &value, &ctc_mac_ctl_enclk);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcHata_f,  &value, &ctc_mac_ctl_enclk);
        cmd = DRV_IOW(CtcMacCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_enclk));
    }
#endif
    return CTC_E_NONE;
}

uint8
_sys_at_mcmac_is_power_up(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  physic_lane_id = 0;
    uint16 psd            = 0;
    uint32 serdes_speed   = 0;

    for (physic_lane_id = 0; physic_lane_id < AT_SERDES_NUM_PER_MCMAC; physic_lane_id++)
    {
        psd = physic_lane_id + AT_SERDES_NUM_PER_MCMAC * (mac_group_id + core_id * AT_MCMAC_NUM_PER_CORE);
        (void) sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed);
        if (serdes_speed)
        {
            return TRUE;
        }
    }

    return FALSE;
}

int32
_sys_at_mac_set_group_enable(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 enable, uint8 is_nw)
{
    if (is_nw)
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_set_group_enable(lchip, core_id, mac_group_id, enable));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_group_enable(lchip, core_id, enable));
    }

    return CTC_E_NONE;
}

uint8
_sys_at_mac_is_power_up(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint8 is_nw)
{
    return (is_nw) ? _sys_at_mcmac_is_power_up(lchip, core_id, mac_group_id) : _sys_at_cpumac_is_power_up(lchip, core_id);
}

int32
sys_at_mac_dynamic_switch_set_group_power(uint8 lchip, sys_dmps_ds_list_t* p_list, uint8 dyn_flag)
{
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint16 lsd          = 0;
    uint8  is_nw        = FALSE;
    sys_dmps_db_upt_info_t port_info  = {0};

    SYS_CONDITION_RETURN((!p_list), CTC_E_INVALID_CONFIG);
    lsd   = p_list->lsd_list[0];
    is_nw = SYS_AT_IS_NW_SERDES(lsd);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,      lsd);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    core_id = SYS_AT_GET_CORE_BY_SERDES(lsd);

    if (SYS_DMPS_DYN_BEFORE_CFG == dyn_flag)
    {
        if (!_sys_at_mac_is_power_up(lchip, core_id, mac_group_id, is_nw))
        {
            /* Before dynamic switch config: dmps_db state: power off, register state: power off. */
            CTC_ERROR_RETURN(_sys_at_mac_set_group_enable(lchip, core_id, mac_group_id, TRUE, is_nw));
        }
    }
    else if (SYS_DMPS_DYN_AFTER_CFG == dyn_flag)
    {
        if (!_sys_at_mac_is_power_up(lchip, core_id, mac_group_id, is_nw))
        {
            /* After dynamic switch config: dmps_db state: power off, register state: power on. */
            CTC_ERROR_RETURN(_sys_at_mac_set_group_enable(lchip, core_id, mac_group_id, FALSE, is_nw));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_pcs_pre_cfg(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{ 
    uint8  psd_lane      = 0;
    uint8  invalid_value = 0;
    uint8  fld_num       = 0;
    uint16 psd_dc        = 0;
    reg_field_info_t fld_info[2] = {{0}};

    CTC_ERROR_RETURN(_sys_at_mac_init_mcmac_pre_config(lchip, core_id, mac_group_id));
    CTC_ERROR_RETURN(_sys_at_mac_init_mcmac_cal_ctrl(lchip, core_id, mac_group_id));
    CTC_ERROR_RETURN(_sys_at_mac_init_mcpcs_400_rx_chan_map(lchip, core_id, mac_group_id));

    for (psd_lane = 0; psd_lane < AT_SERDES_NUM_PER_MCMAC; psd_lane++)
    {
        invalid_value = 8;  /* invalid value: 4`b1000 */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, psd_lane, McPcs800TxPhyLaneCfg_cfgTxPhyLane_0_cfgTxChanId_f, invalid_value);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_tx_phy_lane_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        invalid_value = 8;  /* invalid value: 4`b1000 */
        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, psd_lane, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f,      invalid_value);
        SET_REG_FIELD_INFO(fld_info, fld_num, psd_lane, McPcs800RxPhyLaneCfg_cfgRxPhyLane_0_cfgRxLogicLaneId_f, 2 * invalid_value);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rx_phy_lane_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_rx_cal(lchip, core_id, mac_group_id, psd_lane,
            ((0 == (psd_lane % 2)) ? 3 : 7)));
        CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal(lchip, core_id, mac_group_id, psd_lane,
            ((0 == (psd_lane % 2)) ? 3 : 7)));
        CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_tx_cal(lchip, core_id, mac_group_id, psd_lane + AT_SERDES_NUM_PER_MCMAC,
            ((0 == (psd_lane % 2)) ? 3 : 7)));

        psd_dc = mac_group_id * AT_SERDES_NUM_PER_MCMAC + psd_lane + core_id * AT_SERDES_NUM_PER_CORE;
        CTC_ERROR_RETURN(_sys_at_mac_init_cl73_ability(lchip, core_id, psd_dc));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_group_config(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    SYS_CONDITION_RETURN(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id), CTC_E_INVALID_CONFIG);

#ifdef EMULATION_ENV
#ifndef PCS_ONLY
    uint8  chip_type    = SYS_AT_GET_CHIP_TYPE(lchip);

    if (SYS_AT_IS_1PP(chip_type))
    {
        if ((18 == mac_group_id) || (19 == mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, mac_group_id));
        }
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, mac_group_id));
    }
#endif
#endif
    CTC_ERROR_RETURN(_sys_at_mac_pcs_pre_cfg(lchip, core_id, mac_group_id));

    if (!_sys_at_mcmac_is_power_up(lchip, core_id, mac_group_id))
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_set_group_enable(lchip, core_id, mac_group_id, FALSE));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_init_mac_config(uint8 lchip)
{
    uint8  core_id       = 0;
    uint8  core_num      = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    uint8  mac_group_id  = 0;
    uint8  mac_idx       = 0;
    uint16 mac_id        = DMPS_INVALID_VALUE_U16;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
        {
            /* Filter invalid mac group and config valid mac group */
            SYS_CONDITION_CONTINUE(CTC_E_NONE != _sys_at_mac_group_config(lchip, core_id, mac_group_id));

            if (!_sys_at_mcmac_is_power_up(lchip, core_id, mac_group_id))
            {
                continue;
            }

            for (mac_idx = 0; mac_idx < AT_MAC_ID_NUM_PER_MCMAC; mac_idx++)
            {
                /* loop mac in the mac group */
                mac_id  = core_id * AT_MAC_NUM_PER_CORE + mac_group_id * AT_MAC_ID_NUM_PER_MCMAC + mac_idx;
                if (sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_MAC, mac_id))
                {
                    /* set mac/pcs/hata config */
                    CTC_ERROR_RETURN(_sys_at_mac_set_nw_config_by_mac_id(lchip, mac_id));
                }
            }
        }

#ifdef AT_CPUMAC
        /* init cpumac config */
        CTC_ERROR_RETURN(_sys_at_cpumac_init_mac_config(lchip, core_id));
#endif
    }

#ifdef PCS_ONLY
    CTC_ERROR_RETURN(_sys_at_mac_init_macshim_config(lchip));
#endif
    return CTC_E_NONE;
}

int32
_sys_at_mac_wait_mii_rx_up(uint8 lchip, uint16 dport, uint16 mac_id, uint8 port_type)
{
    uint32 is_up = 0;
    uint32 times = 10000;

    while(--times)
    {
        if(SYS_USW_IS_CPUMAC_PORT(port_type))
        {
            (void)_sys_at_cpumac_get_link_up(lchip, dport, &is_up, 0, SYS_MAC_MII_LINK_FM);
        }
        else
        {
            (void)_sys_at_mac_get_mii_link_status(lchip, mac_id, SYS_MAC_MII_LINK_FM, &is_up);
        }
        if(is_up)
        {
            return CTC_E_NONE;
        }
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "%% RX MII is down! dport %u mac_id %u\n", dport, mac_id);
    return CTC_E_NONE;
}

int32
_sys_at_mac_pcs_multi_lane_reset(uint8 lchip, uint16 lport)
{
    uint16 dport  = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint16 mac_id = DMPS_INVALID_VALUE_U16;
    uint8  port_type = 0;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_MAC, &mac_id));

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_type(lchip, lport, &port_type));

    CTC_ERROR_RETURN(_sys_at_mac_set_pcs_rst(lchip, dport, DMPS_RX, 1));
    CTC_ERROR_RETURN(_sys_at_mac_wait_rx_buf_empty(lchip, mac_id));
    CTC_ERROR_RETURN(_sys_at_mac_set_pcs_rst(lchip, dport, DMPS_RX, 0));
    CTC_ERROR_RETURN(_sys_at_mac_wait_mii_rx_up(lchip, dport, mac_id, port_type));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_mii_rst(uint8 lchip, uint8 core_id, uint16 mac_id, uint8 dir, uint8 reset)
{
    uint8  mac_idx = 0;
    uint32 value   = reset ? 1 : 0;
    uint8  fld_num = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,          mac_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,    mac_idx);

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, ((DMPS_RX == dir) ? SharedMiiResetCfg_cfgSoftRstRx0_f : SharedMiiResetCfg_cfgSoftRstTx0_f), value);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(lchip, core_id, 0, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_pcs_rst(uint8 lchip, uint8 core_id, uint16 mac_id, uint8 dir, uint8 reset, uint16 dport)
{
    uint8  if_mode = 0;
    uint8  mac_idx = 0;
    uint32 value   = reset ? 1 : 0;
    uint8  fld_num = 0;
    uint32 fec_en  = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_en));

    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;

    if ((reset) && (fec_en))
    {
        if ((CTC_CHIP_SERDES_XFI_MODE == if_mode) || (CTC_CHIP_SERDES_XLG_MODE == if_mode))
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mac_idx, if_mode, TRUE));
        }
        else if (CTC_CHIP_SERDES_XXVG_MODE == if_mode)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }

    if ((CTC_CHIP_SERDES_SGMII_MODE == if_mode) || (CTC_CHIP_SERDES_XFI_MODE == if_mode)
            || (CTC_CHIP_SERDES_XXVG_MODE == if_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
    {
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, ((DMPS_RX == dir) ? SharedPcsSoftRst_softRstPcsRx0_f : SharedPcsSoftRst_softRstPcsTx0_f), value);
    }
    else if (CTC_CHIP_SERDES_XLG_MODE == if_mode)
    {
        if (DMPS_RX == dir)
        {
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstXlgRx_f,     value);
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_rxDeskewSoftRst_f, value);
        }
        else
        {
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstXlgTx_f,     value);
        }
    }
    else if (CTC_CHIP_SERDES_LG_MODE == if_mode)
    {
        if (DMPS_RX == dir)
        {
            if (mac_idx < 2)
            {
                SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstXlgRx_f,     value);
                SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_rxDeskewSoftRst_f, value);
            }
            else
            {
                SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstLgRx_f,        value);
                SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_rxDeskewSoftRstLg_f, value);
            }
        }
        else
        {
            if (mac_idx < 2)
            {
                SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstXlgTx_f, value);
            }
            else
            {
                SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstLgTx_f, value);
            }
        }
    }
    else if (CTC_CHIP_SERDES_CG_MODE == if_mode)
    {
        if (DMPS_RX == dir)
        {
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstCgRx_f,      value);
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_rxDeskewSoftRst_f, value);
        }
        else
        {
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, SharedPcsSoftRst_softRstCgTx_f, value);
        }
    }

    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(lchip, core_id, 0, fld_num, fld_info));

    if ((!reset) && (fec_en))
    {
        if ((CTC_CHIP_SERDES_XFI_MODE == if_mode) || (CTC_CHIP_SERDES_XLG_MODE == if_mode))
        {
            CTC_ERROR_RETURN(_sys_at_cpumac_fec_xfi_xlg_cfg(lchip, core_id, value, mac_idx, if_mode, TRUE));
        }
        else if (CTC_CHIP_SERDES_XXVG_MODE == if_mode)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, ResetCtlSharedFec_cfgSoftRstFecRx0_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(lchip, core_id, 0, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_mii_rst(uint8 lchip, uint16 dport, uint8 dir, uint8 reset)
{
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    uint16 mac_id       = DMPS_INVALID_VALUE_U16;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        if(DMPS_RX == dir)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMiiRxSoftReset_f, reset);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f, reset);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_mii_rst(lchip, core_id, mac_id, dir, reset));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% mac %d is not used \n", mac_id);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_pcs_rst(uint8 lchip, uint16 dport, uint8 dir, uint8 reset)
{
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  cfg_type     = McPcs800_TOTAL_CNT;
    uint8  port_type    = 0;
    uint8  if_mode      = 0;
    uint8  fld_num      = 0;
    uint16 mac_id       = DMPS_INVALID_VALUE_U16;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_MAC, &mac_id));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_id_by_dport(lchip, dport, &core_id));

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        cfg_type = (DMPS_RX == dir) ? McPcs800Reset_cfgSoftResetRxChanBmp_f : McPcs800Reset_cfgSoftResetTxChanBmp_f;

        if (CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
        {
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, cfg_type, reset);
            SET_REG_FIELD_INFO(fld_info, fld_num, 4, cfg_type, reset);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, cfg_type, reset);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_pcs_rst(lchip, core_id, mac_id, dir, reset, dport));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% mac %d is not used \n", mac_id);
        return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

int32
_sys_at_mac_set_ignore_fault_cfg(uint8 lchip, uint16 lport, uint32 ignore_en)
{
    uint8  mac_idx          = 0;
    uint8  mac_group_id     = 0;
    uint8  core_id          = 0;
    uint8  port_type        = 0;
    uint8  fld_num          = 0;
    uint16 mac_id           = DMPS_INVALID_VALUE_U16;
    uint32 value            = ignore_en ? 1 : 0;
    uint16 dport            = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    reg_field_info_t fld_info[3]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f, value);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLocalFault_f,  value);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLintFault_f,   value);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiIgnoreRemoteFault0_f, value);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiIgnoreLocalFault0_f,  value);
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiIgnoreLintFault0_f,   value);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid mac %u! port_type %u\n", mac_id, port_type);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

/* set value */
int32
_sys_at_mac_set_mac_pkt_en(uint8 lchip, uint16 dport, uint8 dir, uint32 enable)
{
    uint8  core_id      = 0;
    uint8  mac_idx      = 0;
    uint8  mac_group_id = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    uint32 value        = (0 == enable) ? 0 : 1;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        if(DMPS_RX == dir)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0RxCfg_cfgSgmac0RxPktEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, Sgmac0TxCfg_cfgSgmac0TxPktEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));
        }
    }
    else if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        if(DMPS_RX == dir)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid dport %u, port_type %u\n", dport, port_type);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

/*McMacMiiRxDebugStats.dbgMcMacMiiRx_0.7_dbgMiiRxBuffEmpty*/
int32
_sys_at_mac_wait_rx_buf_empty(uint8 lchip, uint16 dport)
{
    uint8  core_id   = 0;
    uint8  mac_idx   = 0;
    uint8  mac_group_id = 0;
    uint16 mac_id    = 0;
    uint32 times     = 10000;
    uint32 is_empty  = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    while(--times)
    {
        /* check dbgMcMacMiiRx_0..7_dbgMiiRxBuff0Empty */
        SET_REG_SOURCE_FIELD_INFO(fld_info, mac_idx, McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuff0Empty_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_debug_stats(lchip, core_id, mac_group_id, 1, fld_info));
        is_empty = fld_info[0].value;
        if(0 == is_empty)
        {
            continue;
        }

        /* check dbgMcMacMiiRx_0..7_dbgMiiRxBuff1Empty */
        SET_REG_SOURCE_FIELD_INFO(fld_info, mac_idx, McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuff1Empty_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_debug_stats(lchip, core_id, mac_group_id, 1, fld_info));
        is_empty = fld_info[0].value;
        if(0 == is_empty)
        {
            continue;
        }

        /* check dbgMcMacMiiRx_0..7_dbgMiiRxBuff2Empty */
        SET_REG_SOURCE_FIELD_INFO(fld_info, mac_idx, McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuff2Empty_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_debug_stats(lchip, core_id, mac_group_id, 1, fld_info));
        is_empty = fld_info[0].value;
        if(0 == is_empty)
        {
            continue;
        }

        /* check dbgMcMacMiiRx_0..7_dbgMiiRxBuff3Empty */
        SET_REG_SOURCE_FIELD_INFO(fld_info, mac_idx, McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuff3Empty_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_debug_stats(lchip, core_id, mac_group_id, 1, fld_info));
        is_empty = fld_info[0].value;
        if(0 == is_empty)
        {
            continue;
        }

        return CTC_E_NONE;
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% RX MII buf is not empty! mac_id %u\n", mac_id);

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_nw_tx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mac_group_id       = 0;
    uint8  mac_idx            = 0;
    uint8  core_id            = 0;
    uint8  if_mode            = 0;
    uint8  pcs_idx            = 0;
    uint8  fld_num            = 0;
    reg_field_info_t fld_info[2] = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    mac_idx      = p_port_info->mac_idx;
    pcs_idx      = p_port_info->pcs_idx;
    mac_group_id = p_port_info->mac_group;
    if_mode      = p_port_info->if_mode;
    core_id      = p_port_info->core;

    if(en) /* enable mac */
    {
        if (g_at_hata_en)
        {
            /* (II) 1 McHataSoftResetCfg_TxSoftReset */
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataSoftResetCfg_cfgMcHataTxSoftReset_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }

        /* (III) cfgSoftResetTxChanBmp */
        if (CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
        {
            /* 800G: bit 0 and bit 4 should be setted or unresetted together */
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetTxChanBmp_f, 0);
            SET_REG_FIELD_INFO(fld_info, fld_num, 4, McPcs800Reset_cfgSoftResetTxChanBmp_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs800Reset_cfgSoftResetTxChanBmp_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }

        /* (IV) cfgMcMacMiiTxSoftReset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* (V) cfgMcMacTxSendEn */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
    }
    else
    {
        /* (VI) cfgMcMacTxSendEn */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* (VII) cfgMcMacMiiTxSoftReset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_tx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* (VIII) cfgSoftResetTxChanBmp */
        if (CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
        {
            /* 800G: bit 0 and bit 4 should be setted or unresetted together */
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
            SET_REG_FIELD_INFO(fld_info, fld_num, 4, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs800Reset_cfgSoftResetTxChanBmp_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }

        if (g_at_hata_en)
        {
            /* (IX) 1 McHataSoftResetCfg_TxSoftReset */
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataSoftResetCfg_cfgMcHataTxSoftReset_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_nw_rx_en(uint8 lchip, uint16 dport, sys_dmps_db_upt_info_t* p_port_info, uint8 en)
{
    uint8  mac_group_id       = 0;
    uint8  mac_idx            = 0;
    uint8  core_id            = 0;
    uint8  if_mode            = 0;
    uint8  pcs_idx            = 0;
    uint8  fld_num            = 0;
    reg_field_info_t fld_info[2] = {{0}};

    mac_idx      = p_port_info->mac_idx;
    pcs_idx      = p_port_info->pcs_idx;
    mac_group_id = p_port_info->mac_group;
    if_mode      = p_port_info->if_mode;
    core_id      = p_port_info->core;

    if(en) /* enable mac */
    {
        if (g_at_hata_en)
        {
            /* (VI) 1 McHataSoftResetCfg_RxSoftReset */
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataSoftResetCfg_cfgMcHataRxSoftReset_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }

        /* (VII) 1 cfgMcMacMacRxSoftReset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMacRxSoftReset_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        /* (VII) 2 cfgMcMacMiiRxSoftReset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMiiRxSoftReset_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        /* (VIII) cfgSoftResetRxChanBmp */
        if (CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
        {
            /* 800G: bit 0 and bit 4 should be setted or unresetted together */
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetRxChanBmp_f, 0);
            SET_REG_FIELD_INFO(fld_info, fld_num, 4, McPcs800Reset_cfgSoftResetRxChanBmp_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs800Reset_cfgSoftResetRxChanBmp_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }
    else
    {
        /* (II) cfgSoftResetRxChanBmp */
        if (CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
        {
            /* 800G: bit 0 and bit 4 should be setted or unresetted together */
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
            SET_REG_FIELD_INFO(fld_info, fld_num, 4, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, McPcs800Reset_cfgSoftResetRxChanBmp_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_800_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }

        /* (III) check dbgMcMacMiiRx_0~7_dbgMiiRxBuff0Empty0-3 */
        CTC_ERROR_RETURN(_sys_at_mac_wait_rx_buf_empty(lchip, dport));


        /* (IV) 1 cfgMcMacMiiRxSoftReset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMiiRxSoftReset_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        /* (IV) 2 cfgMcMacMacRxSoftReset */
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacRxSoftReset_cfgMcMacMacRxSoftReset_f, 1);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_rx_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));

        if (g_at_hata_en)
        {
            /* (V) 1 McHataSoftResetCfg_RxSoftReset */
            fld_num = 0;
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McHataSoftResetCfg_cfgMcHataRxSoftReset_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mchata_reg_write_soft_rst(lchip, core_id, mac_group_id, fld_num, fld_info));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_nw_mac_en(uint8 lchip, uint16 dport, bool enable)
{
    uint8  idx                = 0;
    uint8  mac_group_id       = 0;
    uint8  core_id            = 0;
    uint16 mac_id             = DMPS_INVALID_VALUE_U16;
    uint8  serdes_num         = 0;
    uint8  pcs_idx            = 0;
    uint32 link_mode          = 0;
    uint8  fld_num            = 0;
    uint8  an_en              = 0;
    reg_field_info_t fld_info[1] = {{0}};
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};
    sys_dmps_db_upt_info_t port_info              = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_LINK_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_AN_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_MODE, link_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_AN_EN,     an_en);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, 
        &serdes_num, physic_serdes));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "%s mac %d\n", (enable ? "Enable" : "Disable"), mac_id);

    if(enable) /* enable mac */
    {
        /* (I) CtcHsCtl_McPcs400PmaCfg_cfgTxAsyncFifoUnderrunEnLane0-3 */
        for(idx = 0; idx < serdes_num; idx++)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx % 4, McPcs400PmaCfg_cfgTxAsyncFifoUnderrunEnLane0_f, 1);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_pma_cfg(lchip, core_id, 2 * mac_group_id + pcs_idx / 4, fld_num, fld_info));
        }

        /*(II~V)*/
        CTC_ERROR_RETURN(_sys_at_mac_set_nw_tx_en(lchip, dport, &port_info, (uint8)enable));
        /*VI~VIII*/
        if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_nw_rx_en(lchip, dport, &port_info, (uint8)enable));
        }
        else
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_pcs_rst(lchip, dport, DMPS_RX, 0));
        }
    }
    else /* disable mac */
    {
        /* (I) CtcHsCtl_McPcs400PmaCfg_cfgTxAsyncFifoUnderrunEnLane0-3 */
        for(idx = 0; idx < serdes_num; idx++)
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx % 4, McPcs400PmaCfg_cfgTxAsyncFifoUnderrunEnLane0_f, 0);
            CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_pma_cfg(lchip, core_id, 2 * mac_group_id + pcs_idx / 4, fld_num, fld_info));
        }

        /*(II~V)*/
        CTC_ERROR_RETURN(_sys_at_mac_set_nw_rx_en(lchip, dport, &port_info, (uint8)enable));
        /*(VI~IX)*/
        CTC_ERROR_RETURN(_sys_at_mac_set_nw_tx_en(lchip, dport, &port_info, (uint8)enable));
    }

    return CTC_E_NONE;
}

int32 _sys_at_mac_set_fec_serdes_speed(uint8 lchip, uint16 dport)
{   
    uint8  if_mode        = CTC_CHIP_SERDES_NONE_MODE;
    uint8  loop           = 0;
    uint8  serdes_num     = 0;
    uint8  fec_type       = 0;
    uint8  ocs            = 0;
    uint16 serdes_list[8] = {0};
    uint32 serdes_speed   = 0;
    uint32 p_speed_value  = 0;
    uint32 speed_value    = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, &serdes_list[0]));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE, fec_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,       ocs);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,     p_speed_value);

    serdes_speed = sys_usw_dmps_get_speed_from_serdes_info(if_mode, fec_type, ocs);
    SYS_USW_SERDES_SPEED_2_VALUE(serdes_speed, speed_value);

    if (p_speed_value != speed_value)
    {
        for(loop = 0; loop < serdes_num; loop++)
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES, serdes_list[loop]);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED, speed_value);
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

            CTC_ERROR_RETURN(_sys_at_serdes_speed_switch_proc(lchip, serdes_list[loop], SERDES_SPEED_0G));
            CTC_ERROR_RETURN(_sys_at_serdes_speed_switch_proc(lchip, serdes_list[loop], serdes_speed));
        }
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_set_fec(uint8 lchip, uint16 lport, void* p_port_info, uint8 fec_val)
{
    uint8  speed_mode  = 0;
    uint8  ocs         = 0;
    uint16 dport       = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint32 speed_value = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    sys_port_api_dmps_info_t* p_info = (sys_port_api_dmps_info_t*)p_port_info;

    CTC_PTR_VALID_CHECK(p_info);

    /*set fec config*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,         ocs);

    SYS_USW_GET_SPEED_VALUE(speed_mode, fec_val, ocs, speed_value);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE,       fec_val);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_VALUE,    speed_value);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_VALUE, speed_value);
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

    if(SYS_DMPS_NETWORK_PORT == p_info->port_type)
    {       
        #ifndef EMULATION_ENV
        /*config serdes */
        CTC_ERROR_RETURN(_sys_at_mac_set_fec_serdes_speed(lchip, dport));
        #endif
        /* set mac/pcs config */
        CTC_ERROR_RETURN(_sys_at_mac_set_nw_config_by_mac_id(lchip, p_info->mac_id));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(p_info->port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_config(lchip, dport, fec_val));
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_port_serdes_tx_en(uint8 lchip, uint16 dport, uint8 en)
{
    uint8  idx     = 0;
    uint8  psd_num = 0;
    uint8  if_mode = CTC_CHIP_SERDES_NONE_MODE;
    uint16 psd[DMPS_MAX_NUM_PER_MODULE]  = {0};
    sys_at_serdes_dev_t    dev           = {0};
    sys_dmps_db_upt_info_t port_info     = {0};

    SYS_CONDITION_RETURN((0 != SDK_WORK_PLATFORM), CTC_E_NONE);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &psd_num, psd));

    _sys_at_get_serdes_dev(lchip, psd[0], &dev);
    for(idx = 0; idx < psd_num; idx++)
    {
        dev.serdes_id = psd[idx];
        CTC_ERROR_RETURN(_sys_at_serdes_set_tx_en(&dev, en));
    }
    if((!en) && ((CTC_CHIP_SERDES_SGMII_MODE == if_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode)))
    {
        sal_udelay(32000);
    }
    
    return CTC_E_NONE;
}

int32 
_sys_at_mac_set_macpcs_en(uint8 lchip, uint16 dport, uint8 port_type, uint8 enable)
{
    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_nw_mac_en(lchip, dport, enable));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_mac_en(lchip, dport, enable));
    }
    
    return CTC_E_NONE;
}

int32 _sys_at_mac_chk_serdes_pll_ready(uint8 lchip, uint16 dport)
{
    
    uint8  loop_idx     = 0;
    uint8  serdes_num   = 0;
    uint16 psd          = 0;
    uint32 speed_value  = 0;
    uint32 serdes_speed = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};
    
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SPEED);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED, speed_value);
    SYS_USW_SERDES_VALUE_2_SPEED(speed_value, serdes_speed);
    
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));

    for (loop_idx = 0; loop_idx < serdes_num; loop_idx ++)
    {
        psd = physic_serdes[loop_idx];
        CTC_ERROR_RETURN(_sys_at_serdes_check_and_recover_pll_ready(lchip, psd, serdes_speed));
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_set_mac_en(uint8 lchip, uint16 lport, void* p_port_info, uint8 enable, uint8 db_upt_flag)
{
    uint16 dport = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    sys_port_api_dmps_info_t* p_info = (sys_port_api_dmps_info_t*)p_port_info;

    uint8 port_type =  p_info->port_type;
    uint8 db_mac_en =  p_info->mac_en;
    uint8 db_an_en  =  p_info->auto_neg_en;

    CTC_PTR_VALID_CHECK(p_info);

    g_print_tbl = 1;
 
    if(1 == db_mac_en && 0 == db_upt_flag && 1 == enable && 0 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_chk_serdes_pll_ready(lchip, dport));
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, TRUE));
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, TRUE));       
    }
    else if(1 == db_mac_en && 0 == db_upt_flag && 0 == enable && 0 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, FALSE));       
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, FALSE));       
    }
    else if(1 == db_mac_en && 0 == db_upt_flag && 0 == enable && 1 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, TRUE));       
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, FALSE));       
    }
    else if(1 == db_mac_en && 0 == db_upt_flag && 1 == enable && 1 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_chk_serdes_pll_ready(lchip, dport));
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, TRUE));
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, TRUE));       
    }
    else if(1 == db_mac_en && 1 == db_upt_flag && 0 == enable && 0 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, FALSE));       
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, FALSE));       
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_mac_en(lchip, lport, FALSE));          
    }
    else if(1 == db_mac_en && 1 == db_upt_flag && 0 == enable && 1 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, FALSE));       
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, FALSE));
        CTC_ERROR_RETURN(sys_usw_dmps_anlt_sm_send_switch_off_msg(lchip, dport));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_mac_en(lchip, lport, FALSE));             
    }
    else if(0 == db_mac_en && 1 == db_upt_flag && 1 == enable && 0 == db_an_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_chk_serdes_pll_ready(lchip, dport));
        CTC_ERROR_RETURN(_sys_at_mac_set_macpcs_en(lchip, dport, port_type, TRUE));       
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, TRUE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_mac_en(lchip, lport, TRUE));             
    }   
    else if(0 == db_mac_en && 1 == db_upt_flag && 1 == enable && 1 == db_an_en)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_anlt_sm_send_anlt_en_msg(lchip, dport));
        CTC_ERROR_RETURN(_sys_at_mac_set_port_serdes_tx_en(lchip, dport, TRUE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_mac_en(lchip, lport, TRUE));
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

/*set tx force fault type*/
int32
_sys_at_mac_set_tx_force_fault(uint8 lchip, uint16 dport, uint32 fault_bmp)
{
    uint8  mac_idx      = 0;
    uint8  mac_group_id = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    uint16 mac_id       = DMPS_INVALID_VALUE_U16;
    uint32 value        = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,             mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,  mac_group_id);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        value   = CTC_FLAG_ISSET(fault_bmp, CTC_PORT_FAULT_FORCE) ? 1 : 0;
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f, value);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        if(CTC_FLAG_ISSET(fault_bmp, CTC_PORT_FAULT_FORCE))
        {
            value |= 0x00000002;
        }
        else
        {
            value &= 0xfffffffd;
        }
        SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiRxPCHLen0_f, value);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is invalid \n", mac_id);
        return CTC_E_INVALID_PORT;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_cl73_ability_param_check(uint8 lchip, uint16 dport, uint32 ability)
{
    uint8  port_type          = 0;
    uint32 idx                = 0;
    uint32 cpumac_unability[] = 
    {
        CTC_PORT_CL73_50GBASE_KR,   CTC_PORT_CL73_50GBASE_CR,   CTC_PORT_CL73_100GBASE_KR2, CTC_PORT_CL73_100GBASE_CR2,
        CTC_PORT_CL73_200GBASE_KR4, CTC_PORT_CL73_200GBASE_CR4, CTC_PORT_CSTM_400GBASE_CR8,
        //CTC_PORT_CL73_100GBASE_KR1,
        //CTC_PORT_CL73_100GBASE_CR1,
        //CTC_PORT_CL73_200GBASE_KR2,
        //CTC_PORT_CL73_200GBASE_CR2,
        //CTC_PORT_CL73_400GBASE_KR4,
        //CTC_PORT_CL73_400GBASE_CR4,
    };
    sys_dmps_db_upt_info_t port_info              = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        for (idx = 0; idx < SYS_AT_MAC_ARRAY_SIZE(cpumac_unability); idx ++)
        {
            if (ability & cpumac_unability[idx])
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% CPUMAC cannot support PAM4! \n");
                return CTC_E_INVALID_CONFIG;
            }
        }
    }

    return CTC_E_NONE;
}

/* support 802.3ap, Auto-Negotiation for Backplane Ethernet */
int32
_sys_at_mac_set_cl73_ability_hw(uint8 lchip, uint8 core_id, uint16 psd, sys_dmps_an_ability_t *p_ability)
{
    uint32 index                = 0;
    uint32 cmd                  = 0;
    uint32 inst_id              = SYS_AT_GET_PSD_SC(psd);
    uint32 cfg_adv_ability[2]   = {0x0, 0x0};
    uint32 cfg_next_page_tx1[2] = {0x0, 0x0};
    uint32 next_page_en         = 1;
    uint32 next_page_num        = ((p_ability->np1_ability0) || (p_ability->np1_ability1)) ? 2 : 0;
    AnethAdvAbility_m adv_ability_reg;
    AnethCtl_m        aneth_ctl_reg;

    /* Read */
    index = DRV_INS(inst_id, 0);
    cmd   = DRV_IOR(AnethAdvAbility_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &adv_ability_reg));
    
    cmd   = DRV_IOR(AnethCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &aneth_ctl_reg));

    DRV_IOR_FIELD(lchip, AnethAdvAbility_t, AnethAdvAbility_cfgAdvAbility_f, cfg_adv_ability,    &adv_ability_reg);
    DRV_IOR_FIELD(lchip, AnethAdvAbility_t, AnethAdvAbility_cfgNextPageTx1_f, cfg_next_page_tx1, &adv_ability_reg);

    /* clear old cl73 ability */
    cfg_adv_ability[0]   &= 0x001F73FF;    
    cfg_adv_ability[1]   &= 0xFFFF0000;
    cfg_next_page_tx1[0] &= 0x0000FFFF;
    cfg_next_page_tx1[1] &= 0xFFFF0000;

    /* set new cl73 ability*/
    cfg_adv_ability[0]   |= p_ability->base_ability0; 
    cfg_adv_ability[1]   |= p_ability->base_ability1;
    cfg_next_page_tx1[0] |= p_ability->np1_ability0;
    cfg_next_page_tx1[1] |= p_ability->np1_ability1;

    /* Mod */
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, AnethAdvAbility_t, inst_id, AnethAdvAbility_cfgAdvAbility_f,  cfg_adv_ability,   &adv_ability_reg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, AnethAdvAbility_t, inst_id, AnethAdvAbility_cfgNextPageTx1_f, cfg_next_page_tx1, &adv_ability_reg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, AnethCtl_t,        inst_id, AnethCtl_cfgAutoNextPageEn_f,     &next_page_en,      &aneth_ctl_reg);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, AnethCtl_t,        inst_id, AnethCtl_cfgNextPageNum_f,        &next_page_num,     &aneth_ctl_reg);

    /* Write */
    cmd   = DRV_IOW(AnethAdvAbility_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &adv_ability_reg));

    cmd   = DRV_IOW(AnethCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &aneth_ctl_reg));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_port_cl73_ability(uint8 lchip, uint16 dport, void* p_ability)
{
    uint8  core_id    = 0;
    uint8  serdes_num = 0;
    uint8  lane_id    = 0;
    sys_dmps_an_ability_t* cl73_ability = p_ability;
    sys_dmps_db_upt_info_t upt_info_p  = {0};
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_id_by_dport(lchip, dport, &core_id));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));
    for(lane_id = 0; lane_id < serdes_num; lane_id++)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_cl73_ability_hw(lchip, core_id, physic_serdes[lane_id], cl73_ability));
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
    DMPS_DB_SET_MAP_INFO(upt_info_p,      DMPS_DB_DPORT,         dport);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_BP_ABILITY0,  cl73_ability->base_ability0);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_BP_ABILITY1,  cl73_ability->base_ability1);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP0_ABILITY0, cl73_ability->np0_ability0);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP0_ABILITY1, cl73_ability->np0_ability1);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP1_ABILITY0, cl73_ability->np1_ability0);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP1_ABILITY1, cl73_ability->np1_ability1);

    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &upt_info_p));
    return CTC_E_NONE;
}

int32
_sys_at_mac_set_cl73_ability(uint8 lchip, uint16 dport, uint32 ctc_ability)
{
    uint8  is_hit     = FALSE;
    uint32 loop_idx   = 0;
    sys_dmps_an_ability_t cl73_ability = {0};
    cl73_ability_ctc_sys_map_tbl_t ability_map_tab[] = 
    {
        /* ctc_cl73_ability                       sys_cl73_ability                                         pointer of cfg_val        */
        {CTC_PORT_CL73_10GBASE_KR,                SYS_PORT_CL73_10GBASE_KR,                                &cl73_ability.base_ability0},
        {CTC_PORT_CL73_40GBASE_KR4,               SYS_PORT_CL73_40GBASE_KR4,                               &cl73_ability.base_ability0},
        {CTC_PORT_CL73_40GBASE_CR4,               SYS_PORT_CL73_40GBASE_CR4,                               &cl73_ability.base_ability0},
        {CTC_PORT_CL73_100GBASE_KR4,              SYS_PORT_CL73_100GBASE_KR4,                              &cl73_ability.base_ability0},
        {CTC_PORT_CL73_100GBASE_CR4,              SYS_PORT_CL73_100GBASE_CR4,                              &cl73_ability.base_ability0},
        {CTC_PORT_CL73_FEC_ABILITY,               SYS_PORT_CL73_FEC_SUP,                                   &cl73_ability.base_ability1},
        {CTC_PORT_CL73_FEC_REQUESTED,             SYS_PORT_CL73_FEC_REQ,                                   &cl73_ability.base_ability1},
        {CTC_PORT_CL73_25GBASE_CRS,               SYS_PORT_CL73_25GBASE_CR_S,                              &cl73_ability.base_ability0},
        {CTC_PORT_CL73_25GBASE_KR,                (SYS_PORT_CL73_25GBASE_KR | SYS_PORT_CL73_25GBASE_KR_S), &cl73_ability.base_ability0},
        {CTC_PORT_CL73_25G_RS_FEC_REQUESTED,      SYS_PORT_CL73_25G_RS_FEC_REQ,                            &cl73_ability.base_ability1},
        {CTC_PORT_CL73_25G_BASER_FEC_REQUESTED,   SYS_PORT_CL73_25G_BASER_FEC_REQ,                         &cl73_ability.base_ability1},
        {CTC_PORT_CSTM_25GBASE_KR1,               SYS_PORT_CSTM_25GBASE_KR1,                               &cl73_ability.np1_ability0},
        {CTC_PORT_CSTM_25GBASE_CR1,               SYS_PORT_CSTM_25GBASE_CR1,                               &cl73_ability.np1_ability0},
        {CTC_PORT_CSTM_50GBASE_KR2,               SYS_PORT_CSTM_50GBASE_KR2,                               &cl73_ability.np1_ability0},
        {CTC_PORT_CSTM_50GBASE_CR2,               SYS_PORT_CSTM_50GBASE_CR2,                               &cl73_ability.np1_ability0},
        {CTC_PORT_CSTM_RS_FEC_ABILITY ,           SYS_PORT_CSTM_CL91_FEC_SUP,                              &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_BASER_FEC_ABILITY,         SYS_PORT_CSTM_CL74_FEC_SUP,                              &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_RS_FEC_REQUESTED,          SYS_PORT_CSTM_CL91_FEC_REQ,                              &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_BASER_FEC_REQUESTED,       SYS_PORT_CSTM_CL74_FEC_REQ,                              &cl73_ability.np1_ability1},
        {CTC_PORT_CL73_50GBASE_KR,                SYS_PORT_CL73_50GBASE_KR,                                &cl73_ability.base_ability1},
        {CTC_PORT_CL73_50GBASE_CR,                SYS_PORT_CL73_50GBASE_CR,                                &cl73_ability.base_ability1},
        {CTC_PORT_CL73_100GBASE_KR2,              SYS_PORT_CL73_100GBASE_KR2,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_100GBASE_CR2,              SYS_PORT_CL73_100GBASE_KR2,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_200GBASE_KR4,              SYS_PORT_CL73_200GBASE_KR4,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_200GBASE_CR4,              SYS_PORT_CL73_200GBASE_CR4,                              &cl73_ability.base_ability1},
        {CTC_PORT_CSTM_400GBASE_CR8,              SYS_PORT_CSTM_400GBASE_CR8,                              &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_LF1_50GR1,                 SYS_PORT_CSTM_LF1_50GR1,                                 &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_LF2_100GR2,                SYS_PORT_CSTM_LF2_100GR2,                                &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_LF3_200GR4,                SYS_PORT_CSTM_LF3_200GR4,                                &cl73_ability.np1_ability1},
        {CTC_PORT_CSTM_LL_RS_FEC_REQ,             SYS_PORT_CSTM_LL_RS_FEC_REQ,                             &cl73_ability.np1_ability1},
    }; 
    sys_dmps_db_upt_info_t upt_info_p  = {0};
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    SYS_MAC_INIT_CHECK();

    /* ctc_cl73_ability --> sys_cl73_ability */
    if (0x0 != ctc_ability)
    {    
        /* param check */
        CTC_ERROR_RETURN(_sys_at_mac_set_cl73_ability_param_check(lchip, dport, ctc_ability));

        /* get old cl73_ability */
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
        DMPS_DB_SET_MAP_INFO(upt_info_p,        DMPS_DB_DPORT,         dport);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_BP_ABILITY0);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_BP_ABILITY1);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP0_ABILITY0);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP0_ABILITY1);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP1_ABILITY0);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP1_ABILITY1);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &upt_info_p));
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_BP_ABILITY0,  cl73_ability.base_ability0);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_BP_ABILITY1,  cl73_ability.base_ability1);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP0_ABILITY0, cl73_ability.np0_ability0);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP0_ABILITY1, cl73_ability.np0_ability1);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP1_ABILITY0, cl73_ability.np1_ability0);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP1_ABILITY1, cl73_ability.np1_ability1);

        /* clear old ability-ext */
        for (loop_idx = 0; loop_idx < SYS_AT_MAC_ARRAY_SIZE(ability_map_tab); loop_idx ++)
        {
            *ability_map_tab[loop_idx].p_ability &= (~ability_map_tab[loop_idx].sys_ability);
        }

        for (loop_idx = 0; loop_idx < SYS_AT_MAC_ARRAY_SIZE(ability_map_tab); loop_idx ++)
        {
            /* if ctc_cl73_ability cfg a certain ability, then set a bit of cfg_val by sys_cl73_ability */
            if (ctc_ability & ability_map_tab[loop_idx].ctc_ability)
            {
                is_hit = TRUE;
                *ability_map_tab[loop_idx].p_ability |= ability_map_tab[loop_idx].sys_ability;
            }
        }
        if (!is_hit)
        {
            return CTC_E_INVALID_PARAM;
        }

        if((cl73_ability.np1_ability0) || (cl73_ability.np1_ability1))
        {
            cl73_ability.base_ability0 |= (SYS_PORT_CL73_NEXT_PAGE);
        }
    }

    /* 2. cfg ability */
    CTC_ERROR_RETURN(_sys_at_mac_set_port_cl73_ability(lchip, dport, (void*)(&cl73_ability)));

    return CTC_E_NONE;
}

int32
sys_at_mac_set_cl73_ability_ext(uint8 lchip, uint16 dport, uint32 ctc_ability)
{
    uint8  is_hit     = FALSE;
    uint32 loop_idx   = 0;
    sys_dmps_an_ability_t cl73_ability = {0};
    cl73_ability_ctc_sys_map_tbl_t ability_map_tab[] = 
    {
        /* ctc_cl73_ability                       sys_cl73_ability                                         pointer of cfg_val        */
        {CTC_PORT_CL73_100GBASE_KR1,              SYS_PORT_CL73_100GBASE_KR1,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_100GBASE_CR1,              SYS_PORT_CL73_100GBASE_CR1,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_200GBASE_KR2,              SYS_PORT_CL73_200GBASE_KR2,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_200GBASE_CR2,              SYS_PORT_CL73_200GBASE_CR2,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_400GBASE_KR4,              SYS_PORT_CL73_400GBASE_KR4,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_400GBASE_CR4,              SYS_PORT_CL73_400GBASE_CR4,                              &cl73_ability.base_ability1},
        {CTC_PORT_CL73_100G_RS_FEC_INT_REQUESTED, SYS_PORT_CL73_100G_RS_FEC_INT_REQ,                       &cl73_ability.base_ability1},
        {CTC_PORT_CSTM_800G_ETC_CR8,              SYS_PORT_CSTM_800GETC_CR8,                               &cl73_ability.np1_ability0},
        {CTC_PORT_CSTM_800G_ETC_KR8,              SYS_PORT_CSTM_800GETC_KR8,                               &cl73_ability.np1_ability0},
    };    
    sys_dmps_db_upt_info_t upt_info_p  = {0};
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    SYS_MAC_INIT_CHECK();
    
    /* ctc_cl73_ability --> sys_cl73_ability */
    if (0x0 != ctc_ability)
    {    
        /* param check */
        CTC_ERROR_RETURN(_sys_at_mac_set_cl73_ability_param_check(lchip, dport, ctc_ability));

        /* get old cl73_ability */
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
        DMPS_DB_SET_MAP_INFO(upt_info_p,        DMPS_DB_DPORT,         dport);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_BP_ABILITY0);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_BP_ABILITY1);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP0_ABILITY0);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP0_ABILITY1);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP1_ABILITY0);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PORT_NP1_ABILITY1);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &upt_info_p));
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_BP_ABILITY0,  cl73_ability.base_ability0);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_BP_ABILITY1,  cl73_ability.base_ability1);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP0_ABILITY0, cl73_ability.np0_ability0);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP0_ABILITY1, cl73_ability.np0_ability1);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP1_ABILITY0, cl73_ability.np1_ability0);
        DMPS_DB_GET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_NP1_ABILITY1, cl73_ability.np1_ability1);

        /* clear old ability-ext */
        for (loop_idx = 0; loop_idx < SYS_AT_MAC_ARRAY_SIZE(ability_map_tab); loop_idx ++)
        {
            *ability_map_tab[loop_idx].p_ability &= (~ability_map_tab[loop_idx].sys_ability);
        }

        /* get ability */
        for (loop_idx = 0; loop_idx < SYS_AT_MAC_ARRAY_SIZE(ability_map_tab); loop_idx ++)
        {
            /* if ctc_cl73_ability cfg a certain ability, then set a bit of cfg_val by sys_cl73_ability */
            if (ctc_ability & ability_map_tab[loop_idx].ctc_ability)
            {
                is_hit = TRUE;
                *ability_map_tab[loop_idx].p_ability |= ability_map_tab[loop_idx].sys_ability;
            }
        }
        
        if (!is_hit)
        {
            return CTC_E_INVALID_PARAM;
        }

        if((cl73_ability.np1_ability0) || (cl73_ability.np1_ability1))
        {
            cl73_ability.base_ability0 |= (SYS_PORT_CL73_NEXT_PAGE);
        }
    }

    /* 2. cfg ability*/
    CTC_ERROR_RETURN(_sys_at_mac_set_port_cl73_ability(lchip, dport, (void*)(&cl73_ability)));
        
    return CTC_E_NONE;
}

/* clear default cl73 local ability, set to none */
int32
_sys_at_mac_init_cl73_ability(uint8 lchip, uint8 core_id, uint16 psd)
{
    sys_dmps_an_ability_t cl73_ability;

    sal_memset(&cl73_ability, 0, sizeof(sys_dmps_an_ability_t));
    CTC_ERROR_RETURN(_sys_at_mac_set_cl73_ability_hw(lchip, core_id, psd, &cl73_ability));

    return CTC_E_NONE;
}

int32
_sys_at_mac_sgmii_set_parallel_detect_en(uint8 lchip, uint16 dport, uint8 enable)
{
    uint8  pcs_idx   = 0;
    uint8  port_type = 0;
    uint8  core_id   = 0;
    uint8  fld_num   = 0;
    uint32 cl37_en   = 0;
    uint32 value     = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);

    /*parameter check*/
    CTC_ERROR_RETURN(_sys_at_mac_get_cl37_auto_neg(lchip, dport, CTC_PORT_PROP_AUTO_NEG_EN, &cl37_en));
    if(!cl37_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Dport %d in force mode, cannot set parallel detect. \n", dport);
        return CTC_E_INVALID_CONFIG;
    }

    /*CPUMAC Port*/
    SYS_CONDITION_RETURN(!SYS_USW_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PARAM);

    value    = enable ? 1 : 0;
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_id_by_dport(lchip, dport, &core_id));
    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));
    
    return CTC_E_NONE;
}

int32
_sys_at_mac_set_parallel_detect_en(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  port_type = 0;
    uint8  if_mode   = 0;
    uint16 mac_id    = SYS_AT_USELESS_ID16;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "dport:0x%04X, value:%d\n", dport, value);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,             mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_MAC, &mac_id));

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();

    if (!SYS_USW_IS_NETWORK_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", mac_id);
        return CTC_E_INVALID_PORT;
    }

    switch(if_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN(_sys_at_mac_sgmii_set_parallel_detect_en(lchip, dport, value ? TRUE : FALSE));
            break;
        default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
    }
    
    return CTC_E_NONE;
}


int32
_sys_at_mac_sgmii_get_parallel_detect_en(uint8 lchip, uint16 dport, uint32 *value)
{
    uint8  pcs_idx    = 0;
    uint8  core_id    = 0;
    uint8  port_type  = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);

    /*CPUMAC Port*/
    SYS_CONDITION_RETURN(!SYS_USW_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PARAM);

    SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Cfg_anParallelDetectEn0_f);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, 1, &fld_info));
    *value = fld_info.value;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_parallel_detect_en(uint8 lchip, uint16 dport, uint32 *p_value)
{
    uint8  port_type  = 0;
    uint8  if_mode    = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);

    if(!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Port %d is not used \n", dport);
        return CTC_E_INVALID_PORT;
    }

    switch(if_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN(_sys_at_mac_sgmii_get_parallel_detect_en(lchip, dport, p_value));
            break;
        default:
            break;
    }

    return CTC_E_NONE;
}


int32
sys_at_mac_set_cl37_en(uint8 lchip, uint16 lport, uint32 enable)
{
    uint8  pcs_idx    = 0;
    uint8  core_id    = 0;
    uint16 dport      = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint8  fld_num    = 0;
    reg_field_info_t     fld_info[1] = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anEnable0_f, (enable ? 1 : 0));
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    return CTC_E_NONE; 
}

int32
sys_at_mac_get_cl37_en(uint8 lchip, uint16 lport, uint32* p_en)
{
    uint32 value     = 0;
    uint8  port_type = 0;
    uint8  pcs_idx   = 0;
    uint8  if_mode   = 0;
    uint8  core_id   = 0;
    uint16 dport     = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_CONDITION_RETURN(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport), CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    SYS_CONDITION_RETURN(!SYS_TMM_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PARAM);
    /* SGMII/QSGMII mode auto neg */
    if((CTC_CHIP_SERDES_SGMII_MODE == if_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_id_by_dport(lchip, dport, &core_id));
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Cfg_anEnable0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, 1, &fld_info));
        value = fld_info.value;
    }
    SYS_USW_VALID_PTR_WRITE(p_en, value);
    return CTC_E_NONE; 
}

int32
sys_at_mac_set_cl37_mode(uint8 lchip, uint16 lport, uint32 value)
{
    uint8  pcs_idx    = 0;
    uint8  core_id    = 0;
    uint16 dport = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint8  fld_num    = 0;
    reg_field_info_t     fld_info[1] = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_anegMode0_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
sys_at_mac_get_cl37_mode(uint8 lchip, uint16 lport, uint32* p_mode)
{
    uint32 value     = 0;
    uint8  port_type = 0;
    uint8  pcs_idx   = 0;
    uint8  if_mode   = 0;
    uint8  core_id   = 0;
    uint16 dport     = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};
    SYS_CONDITION_RETURN(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport), CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    SYS_CONDITION_RETURN(!SYS_TMM_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PARAM);
    /* SGMII/QSGMII mode auto neg */
    if((CTC_CHIP_SERDES_SGMII_MODE == if_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Cfg_anegMode0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, 1, &fld_info));
        value = fld_info.value;
    }
    SYS_USW_VALID_PTR_WRITE(p_mode, value);
    return CTC_E_NONE; 
}

int32
_sys_at_mac_set_rx_rst_condition(uint8 lchip, uint16 dport, uint8 rst_cond)
{
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_LINK_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_EN);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));

    SYS_CONDITION_RETURN(0 == port_info.mac_en, CTC_E_NONE);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "        set_rx_rst: dport %u, rst_cond %u\n", dport, rst_cond);

    switch(rst_cond)
    {
        case RST_PCS_0_MAC_1:
            /*1. set all rx reset*/
            if(SYS_USW_IS_CPUMAC_PORT(port_info.port_type))
            {
                CTC_ERROR_RETURN(_sys_at_cpumac_set_rx_en(lchip, dport, 0));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_at_mac_set_nw_rx_en(lchip, dport, &port_info, 0));
            }
            /*2. release pcs rx reset*/
            CTC_ERROR_RETURN(_sys_at_mac_set_pcs_rst(lchip, dport, DMPS_RX, 0));
            break;
        case RST_PCS_0_MAC_0:
        default:
            /*1. set pcs rx reset*/
            CTC_ERROR_RETURN(_sys_at_mac_set_pcs_rst(lchip, dport, DMPS_RX, 1));
            /*2. release all rx reset*/
            if(SYS_USW_IS_CPUMAC_PORT(port_info.port_type))
            {
                CTC_ERROR_RETURN(_sys_at_cpumac_set_rx_en(lchip, dport, 1));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_at_mac_set_nw_rx_en(lchip, dport, &port_info, 1));
            }
            break;
    }
    return CTC_E_NONE; 
}

int32
_sys_at_mac_set_link_mode(uint8 lchip, uint16 dport, uint32 link_mode)
{
    uint32 cur_link_mode = 0;
    SYS_CONDITION_RETURN(LINK_MODE_BUTT <= link_mode, CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode_by_dport(lchip, dport, &cur_link_mode));
    SYS_CONDITION_RETURN(cur_link_mode == link_mode, CTC_E_NONE);

    CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, 
        (LINK_MODE_STDALONE == link_mode) ? RST_PCS_0_MAC_0 : RST_PCS_0_MAC_1));

    CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_mode_by_dport(lchip, dport, link_mode));

    return CTC_E_NONE; 
}

int32
sys_at_mac_set_link_training_en(uint8 lchip, uint16 psd, uint8 enable)
{
    uint8  loop_idx   = 0;
    uint8  serdes_num = 0;
    uint16 dport      = 0;
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PSD, psd, DMPS_DB_TYPE_PORT, NULL, &dport));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "dport", dport);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "enable", enable);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));
    for (loop_idx = 0; loop_idx < serdes_num; loop_idx ++)
    {
        psd = physic_serdes[loop_idx];
        CTC_ERROR_RETURN(sys_at_serdes_set_link_training_en(lchip, psd, enable));
    }

    CTC_ERROR_RETURN(_sys_at_mac_set_link_mode(lchip, dport, enable ? LINK_MODE_STDALONE : LINK_MODE_PCS_PMA));
    
    return CTC_E_NONE;
}

int32
sys_at_mac_set_cl73_en(uint8 lchip, uint16 lport, uint32 enable, uint8 restart)
{
    uint16 dport = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "dport", dport);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "enable", enable);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "restart", restart);

    /* upd soft sw */
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_cl73_en(lchip, lport, enable));

    /* Trigger ANLT_EN or ANLT_SM_OFF Event */
    CTC_ERROR_RETURN(sys_usw_dmps_anlt_sm_cl73_en_event(lchip, dport, enable));

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl73_en(uint8 lchip, uint16 lport, uint32* p_en)
{
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_cl73_en(lchip, lport, p_en));
    return CTC_E_NONE;
}

int32
sys_at_mac_set_speed(uint8 lchip, uint16 lport, uint8 speed_mode)
{
    uint16 dport = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_speed_mode(lchip, lport, speed_mode));
    CTC_ERROR_RETURN(_sys_at_cpumac_set_sgmii_config(lchip, dport));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_link_intr(uint8 lchip, uint16 dport, uint8 enable)
{
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint32 index        = 0;
    uint32 cmd          = 0;
    uint32 tbl_id       = 0;
    uint32 value[5]     = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,     mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        mac_group_id = 0;
        tbl_id       = CpuMacProcInterruptFunc_t;
        CTC_BIT_SET(value[3], 30 - mac_idx);
        if (3 == mac_idx)
        {
            CTC_BIT_SET(value[3], 31);
        }
        else
        {
            CTC_BIT_SET(value[4], 2 - mac_idx);
        }
    }
    else
    {
        tbl_id       = CtcMacCtlInterruptFunc_t;
        CTC_BIT_SET(value[0], 2 + mac_idx);
        CTC_BIT_SET(value[0], 10 + mac_idx);
    }

    if(enable)
    {
        /*clear link intr*/
        index = DRV_INS(mac_group_id, 1);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, value));
        index = DRV_INS(mac_group_id, 3);
    }
    else
    {
        index = DRV_INS(mac_group_id, 2);
    }

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, value));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                  dport);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_INTR_EN, ((enable)?1:0));
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_unidir_en(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  mac_idx      = 0;
    uint8  mac_group_id = 0;
    uint8  pcs_idx      = 0;
    uint8  if_mode      = 0;
    uint8  core_id      = 0;
    uint8  fld_num      = 0;
    uint8  enable       = value ? 1 : 0;
    uint8  port_type    = 0;
    uint16 lport        = sys_usw_dmps_db_get_lport_by_dport(lchip, dport);
    uint32 an_en_stat   = 0;
    reg_field_info_t fld_info[3]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_CONDITION_RETURN(lport == SYS_DMPS_INVALID_U16, CTC_E_NONE);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    if(!SYS_USW_IS_NETWORK_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used \n");
        return CTC_E_INVALID_PORT;
    }

    /*if auto-neg enable, cannot set unidir enable*/
    if(SYS_MAC_IS_MODE_SUPPORT_CL37(if_mode))
    {
        CTC_ERROR_RETURN(sys_at_mac_get_cl37_en(lchip, lport, &an_en_stat));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_mac_get_cl73_en(lchip, lport, &an_en_stat));
    }
    if(value && an_en_stat)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Dport %u has enable auto-nego, cannot enable unidir! \n", dport);
        return CTC_E_INVALID_CONFIG;
    }

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f, enable);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLocalFault_f,  enable);
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLintFault_f,   enable);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        if((CTC_CHIP_SERDES_SGMII_MODE == if_mode)|| (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
        {
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, pcs_idx, SharedPcsCfg_unidirectionEn0_f, enable);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_cfg(lchip, core_id, 0, fld_num, fld_info));
        }
        else
        {
            sal_memset(fld_info, 0xff, 3 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiIgnoreRemoteFault0_f, enable);
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiIgnoreLocalFault0_f,  enable);
            SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiIgnoreLintFault0_f,   enable);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid port %u! port_type %u\n", dport, port_type);
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,               dport);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_UNIDIR_EN, (value ? TRUE : FALSE));
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

    return CTC_E_NONE;
}

int32
_sys_at_mcmac_set_ipg(uint8 lchip, uint16 dport, uint32 value_raw)
{
    uint8  mac_group_id = 0;
    uint8  if_mode   = 0;
    uint8  mac_idx   = 0;
    uint8  core_id   = 0;
    uint8  port_type = 0;
    uint8  fld_num   = 0;
    uint32 value     = value_raw & 0x000000ff;
    uint32 cfg_en    = (value_raw >> 8) & 0x000000ff;
    sys_dmps_db_upt_info_t port_info = {0};
    reg_field_info_t fld_info[2]     = {{0}};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,     mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,     if_mode);

    if (SYS_DMPS_NETWORK_PORT != port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Port %d is not used \n", dport);
        return CTC_E_INVALID_PORT;
    }

    if((CTC_CHIP_SERDES_SGMII_MODE == if_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode) || 
       (CTC_CHIP_SERDES_QSGMII_MODE == if_mode))
    {
        return CTC_E_INVALID_PARAM;
    }
    else
    {
        if((8 !=value) && (12 != value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Value %d is invalid, only 8 or 12 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }

    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgLen_f,       value);
    SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxCtSuperG2Mod_f, cfg_en);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacRxCtSuperG2Mod_f, cfg_en);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE; 
}

int32
_sys_at_cpumac_set_ipg(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  mac_idx   = 0;
    uint8  core_id   = 0;
    uint8  port_type = 0;
    uint8  fld_num   = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d, value:%d\n", dport, value);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Port %d is not used \n", dport);
        return CTC_E_INVALID_PORT;
    }

    if((8 != value) && (12 != value))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid, only 8 or 12 is permitted.  \n", value);
        return CTC_E_INVALID_PARAM;
    }

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxIpgLen0_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));

    return CTC_E_NONE; 
}

int32
_sys_at_mac_set_ipg(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d, enable:0x%X\n", dport, value);

    SYS_MAC_INIT_CHECK();

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_set_ipg(lchip, dport, value));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_ipg(lchip, dport, value));
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_set_preamble(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  core_id      = 0;
    uint8  mii_idx      = 0;
    uint8  if_mode      = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,     if_mode);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d, value:%d\n", dport, value);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Dport %d is not used \n", dport);
        return CTC_E_INVALID_CONFIG;
    }

    /*check*/
    if(CTC_CHIP_SERDES_SGMII_MODE == if_mode)
    {
        if((2 > value) || (8 < value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid, only 2 to 8 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }
    else if(CTC_CHIP_SERDES_XFI_MODE == if_mode ||
            CTC_CHIP_SERDES_XXVG_MODE == if_mode)
    {
        if((4 != value) && (8 != value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid,only 4 or 8 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedMii0Cfg_cfgMiiTxPreambleLen0_f, value);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mii_idx, fld_num, fld_info));

    return CTC_E_NONE; 
}

int32
_sys_at_mcmac_set_frame_property(uint8 lchip, uint16 dport, ctc_port_property_t port_prop, uint32 value)
{
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  if_mode      = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    reg_field_info_t fld_info[1]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,     mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,     if_mode);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"Dport:%d\n", dport);

    if (SYS_DMPS_NETWORK_PORT != port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Dport %d is not used \n", dport);
        return CTC_E_INVALID_CONFIG;
    }

    if((CTC_PORT_PROP_PREAMBLE != port_prop) && (1 < value))
    {
        return CTC_E_INVALID_PARAM;
    }

    switch (port_prop)
    {
        case CTC_PORT_PROP_PADING_EN:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Tx Padding of Network Port is always enable. \n");
            return CTC_E_INVALID_CONFIG;                         
        case CTC_PORT_PROP_PREAMBLE:
            if((CTC_CHIP_SERDES_SGMII_MODE == if_mode) ||                                                                                                                                                               
               (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode) ||
               (CTC_CHIP_SERDES_QSGMII_MODE == if_mode))
            {
                return CTC_E_INVALID_PARAM;
            }
            else
            {
                if(8 != value)
                {
                    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Preamble len only support 8!\n");
                    return CTC_E_INVALID_PARAM;
                }
            }
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPreambleLen_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
            break;
        case CTC_PORT_PROP_CHK_CRC_EN:
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxCrcCheckEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxStripCrcEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
             break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
            sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxAppendCrcEn_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
        default:
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;  
}

int32
_sys_at_cpumac_set_frame_property(uint8 lchip, uint16 dport, ctc_port_property_t port_prop, uint32 value)
{
    uint8 sgmac_idx     = 0;
    uint8 cfg_index     = 0;
    uint8 core_id       = 0;
    uint16 step         = 0;
    uint32 write_val    = 0;
    uint32 cmd          = 0;
    uint32 tbl_id       = 0;
    uint32 index        = 0;
    void *p_cfg_val     = NULL;
    sys_dmps_db_upt_info_t port_info = {0};
    Sgmac0TxCfg_m              mac_tx_cfg;
    Sgmac0RxCfg_m              mac_rx_cfg;
    uint32 sgmac_prop_en_cfg_mapping[][2] = {
        /*Tbl                         Field              */
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxCrcChkEn_f},     /*0 : CTC_PORT_PROP_CHK_CRC_EN*/
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxTodAppendEn_f},  /*1 : CTC_PORT_PROP_APPEND_TOD_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxPadEn_f},        /*2 : CTC_PORT_PROP_PADING_EN*/   
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxStripCrcEn_f},   /*3 : CTC_PORT_PROP_STRIP_CRC_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxAppendCrcEn_f},  /*4 : CTC_PORT_PROP_APPEND_CRC_EN*/
    };

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          sgmac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);

    switch (port_prop)
    {
        case CTC_PORT_PROP_PREAMBLE:
            CTC_ERROR_RETURN(_sys_at_cpumac_set_preamble(lchip, dport, value));
            return CTC_E_NONE;
        case CTC_PORT_PROP_CHK_CRC_EN:
            cfg_index = 0;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            cfg_index = 1;
            break;  
        case CTC_PORT_PROP_PADING_EN:
            cfg_index = 2;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
            cfg_index = 3;
            break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
            cfg_index = 4;
            break;
        default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
    }

    step   = ((cfg_index >= 2) ? (Sgmac1TxCfg_t - Sgmac0TxCfg_t) : (Sgmac1RxCfg_t - Sgmac0RxCfg_t));
    tbl_id = sgmac_prop_en_cfg_mapping[cfg_index][0] + sgmac_idx * step;

    p_cfg_val = ((cfg_index >= 2) ? ((void *)&mac_tx_cfg) : ((void *)&mac_rx_cfg));
    write_val = value ? 1 : 0;

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, p_cfg_val));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, sgmac_prop_en_cfg_mapping[cfg_index][1], &write_val, p_cfg_val);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, p_cfg_val));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_frame_property(uint8 lchip, uint16 dport, ctc_port_property_t port_prop, uint32 value)
{
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set mac internal property, dport:0x%04X, property:%d, value:%d\n", \
        dport, port_prop, value);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_set_frame_property(lchip, dport, port_prop, value));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_frame_property(lchip, dport, port_prop, value));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
        return CTC_E_INVALID_PORT;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_xpipe_db(uint8 lchip, uint16 lport, uint32 value, uint8 dir_bmp)
{
    uint8  cnt           = 0;
    uint8  free_chan_num = 0;
    uint8  core_id       = 0;
    uint8  pp_id         = 0;
    uint8  dp_id         = 0;
    uint8  txqm_id       = 0;
    uint8  xpipe_en      = 0;
    uint8  xpipe_status  = 0;
    uint8  speed_mode    = 0;
    uint8  chan_num      = 0;
    uint32 speed_value   = 0;
    uint8  inverse_dir   = CHAN_DIR_IS_TX(dir_bmp) ? CHAN_DIR_RX : CHAN_DIR_TX;
    uint16 sub_chan[AT_MAX_XPIPE_CHAN]        = {0};
    uint16 mac_client[AT_MAX_XPIPE_CHAN]      = {0};
    uint16 chan[AT_MAX_XPIPE_CHAN]            = {0};
    uint16 chan_id                            = 0;
    uint16 p_mac_client_id                    = 0;
    uint16 dport                              = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint16 chan_list[DMPS_MAX_NUM_PER_MODULE] = {0};
    sys_dmps_change_chan_info_t info          = {0};
    sys_dmps_db_upt_info_t port_info          = {0};
    sys_dmps_db_upt_info_t upt_info_p         = {0};
    ctc_register_xpipe_mode_t mode            = (ctc_register_xpipe_mode_t) value;
    sys_dmps_db_chan_info_t p_chan_info[AT_MAX_XPIPE_CHAN] = {{0}};

    CTC_ERROR_RETURN((sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport)) ? CTC_E_NONE : CTC_E_INVALID_PORT);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_XPIPE_EN);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_CORE_ID_BY_DIR(dir_bmp));
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_PP_ID_BY_DIR(dir_bmp));
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_DP_ID_BY_DIR(dir_bmp));
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_TXQM_ID_BY_DIR(dir_bmp));
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp));
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, GET_CORE_ID_BY_DIR(dir_bmp),    core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, GET_PP_ID_BY_DIR(dir_bmp),      pp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, GET_DP_ID_BY_DIR(dir_bmp),      dp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, GET_TXQM_ID_BY_DIR(dir_bmp),    txqm_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp), speed_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_VALUE_BY_DIR(dir_bmp),speed_value);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_XPIPE_EN,      xpipe_status);

    xpipe_en = (CTC_XPIPE_MODE_0 == mode) ? FALSE : TRUE;
    /* (tx disable -> tx enable) | (rx disable -> rx enable) */
    if (xpipe_en)
    {
        DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan[0]);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   sub_chan[0]);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), mac_client[0]);

        /* chan_num = 1 if mode is CTC_XPIPE_MODE_1 or CTC_XPIPE_MODE_2 or CTC_XPIPE_MODE_2, otherwise, chan_num = 2 */
        free_chan_num = ((CTC_XPIPE_MODE_1 == mode) || (CTC_XPIPE_MODE_2 == mode) || (CTC_XPIPE_MODE_3 == mode)) ? 1 : 2;
        /* get free chan and mac client */
        CTC_ERROR_RETURN(_sys_at_datapath_get_free_chan(lchip, core_id, pp_id, dp_id, txqm_id,
                            free_chan_num, chan + 1, sub_chan + 1, mac_client + 1, dir_bmp));

        /* config new channel for checking validity */
        for (cnt = 1; cnt < free_chan_num + 1; cnt++)
        {
            SYS_CONDITION_RETURN(DMPS_MAX_CHAN_NUM <= chan[cnt], CTC_E_INVALID_CONFIG);
            (void) sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p);
            DMPS_DB_SET_MAP_INFO(upt_info_p, GET_CHAN_ID_BY_DIR(dir_bmp),            chan[cnt]);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_CORE_ID_BY_DIR(dir_bmp),       core_id);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_PP_ID_BY_DIR(dir_bmp),         pp_id);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_DP_ID_BY_DIR(dir_bmp),         dp_id);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_TXQM_ID_BY_DIR(dir_bmp),       txqm_id);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_SPEED_MODE_BY_DIR(dir_bmp),    speed_mode);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_SPEED_VALUE_BY_DIR(dir_bmp),   speed_value);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), mac_client[cnt]);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   sub_chan[cnt]);
            (void) sys_usw_dmps_db_set_port_info(lchip, &upt_info_p);
        }

        /* check validity */
        info.dst_speed_mode   = speed_mode;
        info.dst_chan_num     = free_chan_num;
        info.dst_chan_list[0] = chan[1];
        info.dst_chan_list[1] = chan[2];
        CTC_ERROR_RETURN(_sys_at_datapath_check(lchip, core_id, pp_id, dp_id, txqm_id, &info, dir_bmp, FALSE));

        /* Update DMPS_DB */
        for (cnt = 0; cnt < free_chan_num + 1; cnt++)
        {
            /* Tx: reverse chan to mac client,  Rx: not reverse */
            p_mac_client_id = CHAN_DIR_IS_TX(dir_bmp) ? mac_client[free_chan_num - cnt] : mac_client[cnt];
            SYS_CONDITION_RETURN(DMPS_MAX_CHAN_NUM <= chan[cnt], CTC_E_INVALID_CONFIG);
            (void) sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p);
            DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_DPORT,                      dport);
            DMPS_DB_SET_MAP_INFO(upt_info_p, GET_CHAN_ID_BY_DIR(dir_bmp),        chan[cnt]);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_XPIPE_EN,         xpipe_status | dir_bmp);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), p_mac_client_id);
            if (0 != cnt)
            {
                /* opf: Assign new channel */
                CTC_ERROR_RETURN(sys_usw_dmps_db_assign_chan_by_dir(lchip, chan[cnt], dir_bmp));
                /* Add mapping between port and new channel */
                DMPS_DB_SET_MAP_UPDATE(upt_info_p);
            }
            (void) sys_usw_dmps_db_set_port_info(lchip, &upt_info_p);
        }
    }
    /* (tx enable -> tx disable) | (rx enable -> rx disable) */
    else
    {
        /* get chan_list */
        sal_memset(chan_list, DMPS_INVALID_VALUE_U8, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport,
            GET_CHAN_TYPE_BY_DIR(dir_bmp), &chan_num, chan_list));
        if (1 == chan_num)
        {
            return CTC_E_NONE;
        }
        else if ((0 == chan_num) || (chan_num > AT_MAX_XPIPE_CHAN))
        {
            return CTC_E_INVALID_CONFIG;
        }

        /* get chan_info list */
        for (cnt = 0; cnt < chan_num; cnt++)
        {
            chan_id = chan_list[cnt];
            SYS_CONDITION_RETURN(DMPS_MAX_CHAN_NUM <= chan_id, CTC_E_INVALID_CONFIG);
            p_chan_info[cnt].chan_id = chan_id;
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, p_chan_info + cnt, dir_bmp));
        }

        /* tx: reverse mac_client */
        if (CHAN_DIR_IS_TX(dir_bmp))
        {
            p_mac_client_id                         = p_chan_info[0].mac_client_id;
            p_chan_info[0].mac_client_id            = p_chan_info[chan_num - 1].mac_client_id;
            p_chan_info[chan_num - 1].mac_client_id = p_mac_client_id;
        }

        for (cnt = 0; cnt < chan_num; cnt++)
        {
            /* update port and chan property */
            (void) sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p);
            DMPS_DB_SET_MAP_INFO(upt_info_p,      DMPS_DB_DPORT,         dport);
            DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_XPIPE_EN, (CHAN_DIR_IS_TXRX(xpipe_status) ? inverse_dir : 0));
            if (0 == cnt)
            {
                DMPS_DB_SET_MAP_INFO(upt_info_p,      GET_CHAN_ID_BY_DIR(dir_bmp),       p_chan_info[cnt].chan_id);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), p_chan_info[cnt].mac_client_id);
                (void) sys_usw_dmps_db_set_port_info(lchip, &upt_info_p);

                CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_chan(lchip, chan_list[cnt], TRUE, dir_bmp, FALSE));
            }
            else
            {
                DMPS_DB_SET_MAP_INFO(upt_info_p,      GET_CHAN_ID_BY_DIR(dir_bmp),       p_chan_info[cnt].chan_id);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_SPEED_MODE_BY_DIR(dir_bmp),    SYS_PORT_SPEED_MAX);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_SPEED_VALUE_BY_DIR(dir_bmp),   0);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), p_chan_info[cnt].mac_client_id);
                (void) sys_usw_dmps_db_set_port_info(lchip, &upt_info_p);

                CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_chan(lchip, chan_list[cnt], FALSE, dir_bmp, FALSE));

                (void) sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p);
                DMPS_DB_SET_MAP_INFO(upt_info_p,      GET_CHAN_ID_BY_DIR(dir_bmp),       p_chan_info[cnt].chan_id);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_CORE_ID_BY_DIR(dir_bmp),       DMPS_INVALID_VALUE_U8);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_PP_ID_BY_DIR(dir_bmp),         DMPS_INVALID_VALUE_U8);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_DP_ID_BY_DIR(dir_bmp),         DMPS_INVALID_VALUE_U8);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_TXQM_ID_BY_DIR(dir_bmp),       DMPS_INVALID_VALUE_U8);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), DMPS_INVALID_VALUE_U16);
                DMPS_DB_SET_PROPERTY_INFO(upt_info_p, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   DMPS_INVALID_VALUE_U16);
                (void) sys_usw_dmps_db_set_port_info(lchip, &upt_info_p);
            }
            /* clear DsQMgrDeqScanBmp */
            CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_deq_scan_bmp(lchip, core_id, pp_id,
                dp_id * SYS_AT_CHAN_NUM_PER_DP + p_chan_info[cnt].sub_chan_id, 0));

            if (0 != cnt)
            {
                /* update mapping */
                (void) sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p);
                DMPS_DB_SET_MAP_UPDATE(upt_info_p);
                DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_DPORT,           dport);
                DMPS_DB_SET_MAP_INFO(upt_info_p, GET_OLD_CHAN_ID_BY_DIR(dir_bmp), p_chan_info[cnt].chan_id);
                (void) sys_usw_dmps_db_set_port_info(lchip, &upt_info_p);

                CTC_ERROR_RETURN(sys_usw_dmps_db_free_chan_by_dir(lchip, p_chan_info[cnt].chan_id, dir_bmp));
            }
        }
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_set_xpipe_en(uint8 lchip, uint16 lport, uint32 value, uint8 dir_bmp)
{
    uint8  chan_num = 0;
    uint16 dport    = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint16 chan_list[DMPS_MAX_NUM_PER_MODULE] = {0};

    CTC_ERROR_RETURN(_sys_at_mac_set_xpipe_db(lchip, lport, value, dir_bmp));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport,
                                                        GET_CHAN_TYPE_BY_DIR(dir_bmp), &chan_num, chan_list));
    CTC_ERROR_RETURN(_sys_at_datapath_xpipe_resource_alloc(lchip, dport, chan_num, chan_list, dir_bmp));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_tailts_en(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    uint32 bit1         = 0;
    uint32 bit0         = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d, enable:0x%X\n", dport, value);

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,          mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,     mac_group_id);

    SYS_CONDITION_RETURN(SYS_DMPS_NETWORK_PORT != port_type, CTC_E_INVALID_PORT);

    /*valid config : 0b00 0b10 0b11    bit 1 ~ en  bit 0 ~ mode*/
    if((0 != value) && (2 != value) && (3 != value))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid config %u!\n", value);
        return CTC_E_INVALID_PARAM;
    }
    bit1 = (value >> 1) & 0x1; //bit 1 en
    bit0 = value & 0x1;        //bit 0 mode

    sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsEn_f,   bit1);
    SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsMode_f, bit0);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxKeepTsEn_f,   bit1);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mac_tx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_cl37_flowctl_ability(uint8 lchip, uint16 dport, uint32 p_capability)
{
    uint8  core_id    = 0;
    uint8  port_type  = 0;
    uint8  if_mode    = 0;
    uint8  pcs_idx    = 0;
    uint32 val_32     = p_capability;
    uint8  fld_num    = 0;
    reg_field_info_t     fld_info[1] = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);

    if(!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Only CPUMAC port support CL37 AN \n");
        return CTC_E_INVALID_CONFIG;
    }

    if((CTC_CHIP_SERDES_SGMII_MODE != if_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != if_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Port mode %u is not supported! \n", if_mode);
        return CTC_E_INVALID_PARAM;
    }
    if(3 < val_32)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid value %u! \n", val_32);
        return CTC_E_INVALID_PARAM;
    }

    switch(val_32)
    {
        case ((!CTC_PORT_PAUSE_ABILITY_TX_EN) & (!CTC_PORT_PAUSE_ABILITY_RX_EN)):
            val_32 = SYS_AT_ASMDIR_0_PAUSE_0;
            break;
        case CTC_PORT_PAUSE_ABILITY_TX_EN:
            val_32 = SYS_AT_ASMDIR_1_PAUSE_0;
            break;
        case CTC_PORT_PAUSE_ABILITY_RX_EN:
            val_32 = SYS_AT_ASMDIR_1_PAUSE_1;
            break;
        case (CTC_PORT_PAUSE_ABILITY_TX_EN | CTC_PORT_PAUSE_ABILITY_RX_EN):
        default:
            val_32 = SYS_AT_ASMDIR_0_PAUSE_1;
            break;
    }

    sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info, fld_num, 0, SharedPcsSgmii0Cfg_localPauseAbility0_f, val_32);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, fld_num, fld_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_group_check_bw(uint8 lchip, uint8 core_id, uint8 mac_group_id, sys_dmps_ds_list_t* p_list)
{
    uint8  cnt              = 0;
    uint8  remote_mac_group = 0;
    uint8  fec_type         = SYS_DMPS_FEC_TYPE_NONE;
    uint16 core_pll         = 0;
    uint16 psd              = 0;
    uint32 speed            = 0;
    uint32 serdes_speed     = 0;
    uint32 speed_sum        = 0;
    uint32 remote_speed_sum = 0;

    /* 1. check speed_sum for pg_low or dcm_pg_low */
    if ((AT_CHIP_IS_SERDES_PG_LOW(lchip)) || (AT_CHIP_IS_SERDES_DCM_PG_LOW(lchip)))
    {
        for (cnt = 0; cnt < AT_SERDES_NUM_PER_MCMAC; cnt++)
        {
            psd = core_id * SYS_AT_NW_SERDES_NUM_PER_CORE + mac_group_id * AT_SERDES_NUM_PER_MCMAC + cnt;
            SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed));
            serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);
            speed_sum += serdes_speed;
        }

        if (p_list)
        {
            for (cnt = 0; cnt < p_list->lsd_num; cnt++)
            {
                CTC_ERROR_RETURN(sys_usw_dmps_db_get_single_relative_id(lchip, DMPS_DB_TYPE_LSD, p_list->lsd_list[cnt], DMPS_DB_TYPE_PSD, &psd));
                CTC_ERROR_RETURN(sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed));
                serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);
                speed_sum -= serdes_speed;
            }

            fec_type =  (SYS_DMPS_IS_PAM4_MODE(p_list->dst_mode)) ? SYS_DMPS_FEC_TYPE_RS544 : SYS_DMPS_FEC_TYPE_NONE;
            speed    = sys_usw_dmps_get_speed_from_serdes_info(p_list->dst_mode, fec_type, p_list->ovclk);
            SYS_USW_SERDES_SPEED_2_VALUE(speed, serdes_speed);
            serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);

            speed_sum += (p_list->lsd_num * serdes_speed);
        }

        if (speed_sum > AT_SERDES_PG_LOW_MAX_SPEED_PER_MCMAC)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Speed Sum of mac group %d is higher than 400G, cannot support!\n", mac_group_id);
            return CTC_E_NOT_SUPPORT;
        }
    }

    /* 2. check speed_sum for 1to2 group in 900M */
    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);

    if ((900 == core_pll) && (SYS_AT_IS_1TO2_GROUP(lchip, mac_group_id)))
    {
        /* 2.1 check if mac group is 1to2 group or not */
        remote_mac_group = SYS_AT_GET_REMOTE_GROUP(lchip, mac_group_id);
        SYS_CONDITION_RETURN((SYS_AT_USELESS_ID8 == remote_mac_group), CTC_E_NONE);

        /* 2.2 get local_speed_sum */
        for (cnt = 0; cnt < AT_SERDES_NUM_PER_MCMAC; cnt++)
        {
            psd = core_id * SYS_AT_NW_SERDES_NUM_PER_CORE + mac_group_id * AT_SERDES_NUM_PER_MCMAC + cnt;
            SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed));
            serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);
            speed_sum += serdes_speed;
        }

        if (p_list)
        {
            for (cnt = 0; cnt < p_list->lsd_num; cnt++)
            {
                CTC_ERROR_RETURN(sys_usw_dmps_db_get_single_relative_id(lchip, DMPS_DB_TYPE_LSD, p_list->lsd_list[cnt], DMPS_DB_TYPE_PSD, &psd));
                CTC_ERROR_RETURN(sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed));
                serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);
                speed_sum -= serdes_speed;
            }

            fec_type =  (SYS_DMPS_IS_PAM4_MODE(p_list->dst_mode)) ? SYS_DMPS_FEC_TYPE_RS544 : SYS_DMPS_FEC_TYPE_NONE;
            speed    = sys_usw_dmps_get_speed_from_serdes_info(p_list->dst_mode, fec_type, p_list->ovclk);
            SYS_USW_SERDES_SPEED_2_VALUE(speed, serdes_speed);
            serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);

            speed_sum += (p_list->lsd_num * serdes_speed);
        }

        /* 2.3 get remote_speed_sum */
        for (cnt = 0; cnt < AT_SERDES_NUM_PER_MCMAC; cnt++)
        {
            psd = core_id * SYS_AT_NW_SERDES_NUM_PER_CORE + remote_mac_group * AT_SERDES_NUM_PER_MCMAC + cnt;
            SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_serdes_speed(lchip, psd, &serdes_speed));
            serdes_speed = SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed);
            remote_speed_sum += serdes_speed;
        }

        /* 2.4 check valid of local and remote spped_sum */
        if (((speed_sum > (AT_SERDES_PG_LOW_MAX_SPEED_PER_MCMAC / 2)) && (remote_speed_sum > 0)) ||
            ((speed_sum > 0) && (remote_speed_sum > (AT_SERDES_PG_LOW_MAX_SPEED_PER_MCMAC / 2))))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Speed Sum of mac group %d is out of limitation!\n", mac_group_id);
            return CTC_E_NOT_SUPPORT;
        }
    }

    return CTC_E_NONE;
}

/* get dynamic switch dport */
int32
_sys_at_mac_get_dynamic_switch_list(uint8 lchip, uint16 physical_serdes, sys_dmps_ds_list_t* target)
{
    uint8  if_mode        = 0;
    uint8  is_dyn         = 0;
    uint8  dst_serdes_num = 0;
    uint8  src_serdes_num = 0;
    uint8  serdes_num     = 0;
    uint8  dport_num      = 0;
    uint8  port_type      = 0;
    uint8  fec_type       = 0;
    uint8  xpipe_en       = 0;
    uint8  chip_type      =  SYS_AT_GET_CHIP_TYPE(lchip);
    uint16 dport          = 0;
    uint16 chan_id        = 0;
    uint16 logical_serdes = 0;
    uint16 end_serdes     = 0;
    uint16 start_serdes   = 0;
    uint16 speed          = 0;
    uint32 support_speed  = 0;
    ctc_chip_serdes_mode_t  src_mode = 0;
    ctc_chip_serdes_mode_t  dst_mode = target->dst_mode;
    sys_dmps_db_upt_info_t port_info = {0};
    sys_dmps_db_cpumac_map_t p_map   = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES, physical_serdes);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT,        dport);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES, logical_serdes);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);

    /* get source mode */
    if (!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
    {
        src_mode = CTC_CHIP_SERDES_NONE_MODE;
    }
    else
    {
        src_mode = if_mode;
    }

    SYS_AT_GET_SERDES_NUM_BY_MODE(src_mode, src_serdes_num);
    SYS_AT_GET_SERDES_NUM_BY_MODE(dst_mode, dst_serdes_num);
    fec_type = SYS_DMPS_IS_PAM4_MODE(dst_mode) ? SYS_DMPS_FEC_TYPE_RS544 : SYS_DMPS_FEC_TYPE_NONE;

    /* get logical serdes list */
    if ((CTC_CHIP_SERDES_NONE_MODE == src_mode) && (CTC_CHIP_SERDES_NONE_MODE == dst_mode))
    {
        target->lsd_num = 0;
    }
    else
    {
        serdes_num      = (src_serdes_num > dst_serdes_num) ? src_serdes_num : dst_serdes_num;
        logical_serdes  = logical_serdes - logical_serdes % serdes_num;
        target->lsd_num = 0;
        while (target->lsd_num < serdes_num)
        {
            target->lsd_list[target->lsd_num] = logical_serdes + target->lsd_num;

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES, target->lsd_list[target->lsd_num]);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_IS_DYN);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_IS_DYN, is_dyn);
            /* check whether serdes supports dynamic switch */
            if (SYS_SERDES_DYN_FORBID_ALL == is_dyn)
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Logic serdes %u fobid dynamic switch!\n", target->lsd_list[target->lsd_num]);
                return CTC_E_NOT_SUPPORT;
            }
            support_speed  = _sys_at_datapath_get_serdes_support_speed_bmp(lchip, chip_type, target->lsd_list[target->lsd_num]);
            speed          = sys_usw_dmps_get_speed_from_serdes_info(dst_mode, fec_type, CTC_CHIP_SERDES_OCS_MODE_NONE);
            if (!((1 << speed) & support_speed))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Serdes cannot support this speed!  \n");
                return CTC_E_INVALID_CONFIG;
            }
            target->lsd_num++;
        }
    }

    start_serdes = logical_serdes;
    end_serdes   = logical_serdes + target->lsd_num;

    /* get dport list */
    while (logical_serdes < end_serdes)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES, logical_serdes);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_XPIPE_EN);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT,        dport);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_XPIPE_EN, xpipe_en);

        if (xpipe_en)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Port % d with xpipe enable cannot support dynamic switch!\n", dport);
            return CTC_E_NOT_SUPPORT;
        }

        if (!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
        {
            logical_serdes++;
            continue;
        }
        else
        {
            SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, serdes_num);
            target->src_dport_list[target->src_dport_num] = dport;

            /* check validity of network port */
            if ((SYS_DMPS_NETWORK_PORT == port_type) && (!SYS_AT_IS_MODE_VALID_NW(target->dst_mode)))
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Dport %u donnot support the mode!\n", dport);
                return CTC_E_NOT_SUPPORT;
            }

            /* check validity of cpumac port */
            if ((SYS_USW_IS_CPUMAC_PORT(port_type)) && (!SYS_AT_IS_MODE_VALID_CPUMAC(target->dst_mode)))
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Dport %u donnot support the mode!\n", dport);
                return CTC_E_NOT_SUPPORT;
            }

            target->src_dport_num++;
            logical_serdes += serdes_num;

        }
    }

    /* get chan list */
    for(dport_num = 0; dport_num < target->src_dport_num; dport_num++)
    {
        dport = target->src_dport_list[dport_num];
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));
        target->chan_info.src_chan_list[target->chan_info.src_chan_num] = chan_id;
        target->chan_info.src_chan_num++;
    }

    if (CTC_CHIP_SERDES_NONE_MODE == dst_mode)
    {
        return CTC_E_NONE;
    }

    /* get dst dport and chan list */
    logical_serdes = start_serdes;
    while (logical_serdes < end_serdes)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_get_port_chan_by_serdes(lchip, logical_serdes, &chan_id, &dport));
        if (!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_PORT, dport))
        {
            return CTC_E_INVALID_PARAM;
        }

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
        target->dst_dport_list[target->dst_dport_num] = dport;
        target->dst_dport_num++;
        if (!SYS_AT_IS_NW_SERDES(logical_serdes))
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_cpumac_map(lchip, (logical_serdes - SYS_AT_NW_SERDES_NUM), &p_map));
            if (!p_map.is_network)
            {
                chan_id = SYS_AT_CHAN_CPUMAC_START + (logical_serdes - SYS_AT_NW_SERDES_NUM);
            }
        }
        /*if (SYS_DMPS_CPU_MAC_PORT == port_type)
        {
            chan_id = SYS_AT_CHAN_CPUMAC_START + (logical_serdes - SYS_AT_NW_SERDES_NUM);
        }*/
        target->chan_info.dst_chan_list[target->chan_info.dst_chan_num] = chan_id;
        target->chan_info.dst_chan_num++;

        /* check validity of network port */
        if ((SYS_DMPS_NETWORK_PORT == port_type) && (!SYS_AT_IS_SUPPORT_NW(target->dst_mode)))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Dport %u donnot support the mode!\n", dport);
            return CTC_E_NOT_SUPPORT;
        }

        /* check validity of cpumac port */
        if ((SYS_USW_IS_CPUMAC_PORT(port_type)) && (!SYS_AT_IS_SUPPORT_CPUMAC(target->dst_mode)))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Dport %u donnot support the mode!\n", dport);
            return CTC_E_NOT_SUPPORT;
        }
        logical_serdes += dst_serdes_num;
    }

    return CTC_E_NONE;
}

/* Dynamic Switch */
int32
sys_at_mac_dynamic_switch_get_list(uint8 lchip, uint16 lport, void* p_mode, void* p_ds_list)
{
    uint8  port_type = 0;
    uint8  core_id   = 0;
    uint8  mac_group = 0;
    uint16 psd       = 0;
    uint16 lsd       = 0;
    uint16 dport     = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    ctc_chip_serdes_mode_t dst_mode  = CTC_CHIP_SERDES_NONE_MODE;
    sys_dmps_db_upt_info_t port_info = {0};
    ctc_port_if_mode_t*    if_mode   = (ctc_port_if_mode_t*)p_mode;
    sys_dmps_ds_list_t*    p_list    = (sys_dmps_ds_list_t*)p_ds_list;
    
    SYS_CONDITION_RETURN(!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_PORT, dport), CTC_E_INVALID_PARAM);

    SYS_DMPS_GET_SERDES_MODE_BY_IFMODE(((sys_port_speed_t) if_mode->speed), if_mode->interface_type, dst_mode);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_AN_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if((SYS_USW_IS_CPUMAC_PORT(port_type)) && (SYS_DMPS_IS_PAM4_MODE(dst_mode)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% CPUMAC connot support the mode \n");
        return CTC_E_PARAM_CONFLICT;
    }

    if (CTC_CHIP_MAX_SERDES_MODE == dst_mode)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Interface speed and type not match \n");
        return CTC_E_PARAM_CONFLICT;
    }

    if(CTC_E_NONE != sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_PSD, &psd))
    {
        /* if port type of the dport is NONE */
        CTC_ERROR_RETURN(_sys_at_datapath_get_serdes_chan_by_lport(lchip, dport, NULL, &lsd));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_LSD, lsd,
            DMPS_DB_TYPE_PSD, NULL, &psd));
    }

    p_list->ovclk    = CTC_CHIP_SERDES_OCS_MODE_NONE;
    p_list->dst_mode = dst_mode;
    SYS_DMPS_GET_PORT_SPEED(dst_mode, p_list->chan_info.dst_speed_mode);
    CTC_ERROR_RETURN(_sys_at_mac_get_dynamic_switch_list(lchip, psd, p_list));

    core_id   = SYS_AT_GET_CORE_BY_NW_SERDES(p_list->lsd_list[0]);
    mac_group = SYS_AT_GET_MAC_GROUP_BY_LSD_DC(p_list->lsd_list[0]);

    /* 2. check param */
    CTC_ERROR_RETURN(_sys_at_mac_group_check_bw(lchip, core_id, mac_group, p_list));
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch_check(lchip, p_list));

    return CTC_E_NONE;
}

int32
sys_at_mac_dynamic_switch_set_config(uint8 lchip, void* p_ds_list, uint32 option_bmp)
{
    uint8 idx = 0;
    uint16 dport = 0;
    uint8 is_switch_serdes = CTC_IS_BIT_SET(option_bmp, DMPS_DS_OPTION_SERDES_SWITCH);
    sys_dmps_ds_list_t* p_list = (sys_dmps_ds_list_t*)p_ds_list;
    /* 4. switch database and config register */
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch(lchip, p_list, is_switch_serdes));

    SYS_CONDITION_RETURN(p_list->dst_dport_num > SYS_DATAPATH_DS_MAX_PORT_NUM, CTC_E_INVALID_PARAM);

    if (CTC_IS_BIT_SET(option_bmp, DMPS_DS_OPTION_CLEAR_CL73))
    {
        for(idx = 0; idx < p_list->dst_dport_num; idx++)
        {
            dport = p_list->dst_dport_list[idx];
            ///TODO: get cl73 en
            CTC_ERROR_RETURN(sys_usw_dmps_anlt_sm_send_switch_off_msg(lchip, dport));
            ///TODO: set cl73 db
        }
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_dynamic_switch_serdes_get_list(uint8 lchip, void* p_serdes_info, void* p_ds_list)
{
    uint8  core_id   = 0;
    uint8  mac_group = 0;
    uint8  is_valid[CTC_CHIP_MAX_SERDES_MODE][CTC_CHIP_MAX_SERDES_OCS_MODE] =
    {
    /*  NONE   11_06  12_12  12_58  27_27  10_6   26_56  26_52   26_9  36_36  36_76  11_06_11 12_58_12 51_56  52_71  20_625 103_12 105_42 */
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_NONE_MODE*/
       {TRUE , TRUE , TRUE , TRUE , FALSE, TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, TRUE ,   TRUE ,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XFI_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_SGMII_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XSGMII_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_QSGMII_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XAUI_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_DXAUI_MODE*/
       {TRUE , TRUE , TRUE , TRUE , FALSE, TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, TRUE ,   TRUE ,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XLG_MODE*/
       {TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, TRUE , TRUE , TRUE , TRUE , TRUE , FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_CG_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_2DOT5G_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_USXGMII0_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_USXGMII1_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_USXGMII2_MODE*/
       {TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, TRUE , TRUE , TRUE , TRUE , TRUE , FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XXVG_MODE*/
       {TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, TRUE , TRUE , TRUE , TRUE , TRUE , FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_LG_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_100BASEFX_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, TRUE , FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_LG_R1_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, TRUE , FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_CG_R2_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, TRUE , FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_CCG_R4_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, TRUE , FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_CDG_R8_MODE*/
       {TRUE,  FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XLG_R2_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, TRUE }, /*CTC_CHIP_SERDES_CG_R1_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, TRUE }, /*CTC_CHIP_SERDES_CCG_R2_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, TRUE }, /*CTC_CHIP_SERDES_CDG_R4_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, TRUE }, /*CTC_CHIP_SERDES_DCCCG_R8_MODE*/
       {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_PHY_MODE*/
       {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_RGMII_MODE*/
       {TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,   FALSE,   FALSE, FALSE, FALSE, FALSE, FALSE}, /*CTC_CHIP_SERDES_XLG_R1_MODE*/
    };
    ctc_chip_serdes_info_t* p_info = (ctc_chip_serdes_info_t*)p_serdes_info;
    sys_dmps_ds_list_t* p_list = (sys_dmps_ds_list_t*)p_ds_list;

    if(!is_valid[p_info->serdes_mode][p_info->overclocking_speed])
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% The mode is not support! \n");
        return CTC_E_INVALID_CONFIG;
    }

    /* 1. get logical serdes, dport, chan list with dynamic switch */
    p_list->ovclk    = p_info->overclocking_speed;
    p_list->dst_mode = p_info->serdes_mode;
    SYS_DMPS_GET_PORT_SPEED(p_info->serdes_mode, p_list->chan_info.dst_speed_mode);
    CTC_ERROR_RETURN(_sys_at_mac_get_dynamic_switch_list(lchip, p_info->serdes_id, p_list));
    core_id   = SYS_AT_GET_CORE_BY_NW_SERDES(p_list->lsd_list[0]);
    mac_group = SYS_AT_GET_MAC_GROUP_BY_LSD_DC(p_list->lsd_list[0]);

    /* 2. check param */
    CTC_ERROR_RETURN(_sys_at_mac_group_check_bw(lchip, core_id, mac_group, p_list));
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch_check(lchip, p_list));

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_ignore_fault_cfg(uint8 lchip, uint16 lport, uint32* p_ignore_en)
{
    uint8  mac_idx          = 0;
    uint8  mac_group_id     = 0;
    uint8  core_id          = 0;
    uint8  pcs_idx          = 0;
    uint8  if_mode          = 0;
    uint8  port_type        = 0;
    uint16 dport            = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint32 value            = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,  mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_tx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        if((CTC_CHIP_SERDES_SGMII_MODE == if_mode)|| (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, pcs_idx, SharedPcsCfg_unidirectionEn0_f);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_cfg(lchip, core_id, 0, 1, &fld_info));
        }
        else
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Cfg_cfgMiiIgnoreLocalFault0_f);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, mac_idx, 1, &fld_info));
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid port %u! port_type %u\n",
            dport, port_type);
        return CTC_E_INVALID_PARAM;
    }
    value = fld_info.value;
    SYS_USW_VALID_PTR_WRITE(p_ignore_en, (value != 0 ? TRUE : FALSE));

    return CTC_E_NONE;
}


/* get value */
int32
_sys_at_mac_get_mac_pkt_en(uint8 lchip, uint16 dport, uint8 dir, uint32* p_enable)
{
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  port_type    = 0;
    uint8  mac_idx      = 0;
    uint32 value        = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,  mac_group_id);

    if(SYS_USW_IS_CPUMAC_PORT(port_type)) /*cpumac*/
    {
        if(DMPS_RX == dir)
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, Sgmac0RxCfg_cfgSgmac0RxPktEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sgmac_rx_cfg(lchip, core_id, 0, mac_idx, 1, &fld_info));
        }
        else
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, Sgmac0RxCfg_cfgSgmac0RxPktEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sgmac_tx_cfg(lchip, core_id, 0, mac_idx, 1, &fld_info));
        }
    }
    else /*NW*/
    {
        if(DMPS_RX == dir)
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_rx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
        }
        else
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_tx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
        }
    }

    value = fld_info.value;
    SYS_USW_VALID_PTR_WRITE(p_enable, value);

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_pcs_link_status(uint8 lchip, uint16 dport, uint32* p_is_up)
{
    uint8  pcs_idx     = 0;
    uint8  if_mode     = 0;
    uint8  core_id     = 0;
    uint8  port_type   = 0;
    uint8  fec_type    = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint32 value       = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    SharedPcsCgStatus_m share_pcs_status;

    SYS_CONDITION_RETURN(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport), CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE, fec_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,  if_mode);

    SYS_CONDITION_RETURN(!SYS_USW_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PORT);

    switch(if_mode)
    {
        case CTC_CHIP_SERDES_CG_MODE:
            tbl_id = SharedPcsCgStatus_t;
            fld_id = SharedPcsCgStatus_cgPcsAlignStatus_f;
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            if (SYS_DMPS_FEC_TYPE_RS528 == fec_type)
            {
                tbl_id = GlobalStatusSharedFec_t;
                fld_id = GlobalStatusSharedFec_dbgSharedFecAlignStatus0_f + pcs_idx *
                        (GlobalStatusSharedFec_dbgSharedFecAlignStatus1_f - GlobalStatusSharedFec_dbgSharedFecAlignStatus0_f);
            }
            else
            {
                if(2 <= pcs_idx)
                {
                    tbl_id = SharedPcsLgStatus_t;
                    fld_id = SharedPcsLgStatus_lgPcs1AlignStatus_f;
                }
                else
                {
                    tbl_id = SharedPcsXlgStatus_t;
                    fld_id = SharedPcsXlgStatus_alignStatus0_f;
                }
            }
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            tbl_id = SharedPcsXlgStatus_t;
            fld_id = SharedPcsXlgStatus_alignStatus0_f;
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
        case CTC_CHIP_SERDES_XXVG_MODE:
            tbl_id = SharedPcsXfi0Status_t + (SharedPcsXfi1Status_t - SharedPcsXfi0Status_t)*pcs_idx;    
            fld_id = SharedPcsXfi0Status_xfiSyncStatus0_f;
            break;
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            tbl_id = SharedPcsSgmii0Status_t + (SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t)*pcs_idx;    
            fld_id = SharedPcsSgmii0Status_sgmiiSyncStatus0_f;
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    cmd      = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &share_pcs_status));

    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &share_pcs_status);

    SYS_USW_VALID_PTR_WRITE(p_is_up, value); 

    return CTC_E_NONE;
}

int32
_sys_at_mcmac_get_pcs_link_status(uint8 lchip, uint16 dport, uint32* p_is_up)
{
    uint8  core_id      = 0;
    uint8  pcs_idx      = 0;
    uint8  mac_group_id = 0;
    uint32 value        = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,  mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);

    SET_REG_SOURCE_FIELD_INFO(&fld_info, pcs_idx % 4, McPcs400RxChanMon_monRxChan_0_monRxSyncStatus_f);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_read_400_rx_chan_mon(lchip, core_id, 2 * mac_group_id + pcs_idx / 4, 1, &fld_info));
    value = fld_info.value;

    SYS_USW_VALID_PTR_WRITE(p_is_up, value); 

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_pcs_link_status(uint8 lchip, uint16 dport, uint32* p_is_up)
{
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    CTC_PTR_VALID_CHECK(p_is_up);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);

    if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        /* cpumac */
        CTC_ERROR_RETURN(_sys_at_cpumac_get_pcs_link_status(lchip, dport, p_is_up));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_get_pcs_link_status(lchip, dport, p_is_up));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_mii_link_status(uint8 lchip, uint16 mac_id, uint8 mii_link_type, uint32* p_value)
{
    uint8  mac_group_id = 0;
    uint8  core_id = 0;
    uint8  mac_idx = 0;
    uint32 fld_id  = 0;
    uint32 val32   = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,             mac_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,  mac_group_id);

    fld_id = (SYS_MAC_MII_LINK_RAW == mii_link_type) ? McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxLinkStatusRaw_f : 
             McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxLinkStatus_f;
    SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, fld_id);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_debug_stats(lchip, core_id, mac_group_id, 1, &fld_info));
    val32 = fld_info.value;

    SYS_USW_VALID_PTR_WRITE(p_value, val32);

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_mac_en(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  mac_en  = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_EN,        mac_en);
    *p_value = mac_en;
    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_sgmii_link_status(uint8 lchip, uint8 type, uint16 dport, uint32* p_value)
{
    uint8  mii_idx   = 0;
    uint8  pcs_idx   = 0;
    uint8  core_id   = 0;
    uint8  port_type = 0;
    uint32 value     = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    /*need not read dbgMiiRxFaultType0 when port less than 10G*/
    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, mii_idx, 1, &fld_info));
        value = fld_info.value;

        *p_value = (value)?TRUE:FALSE;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Status_codeErrCnt0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_status(lchip, core_id, 0, pcs_idx, 1, &fld_info));
        value = fld_info.value;

        *p_value = value;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, mii_idx, 1, &fld_info));
        value = fld_info.value;

        *p_value = (value)?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_xfi_xxvg_link_status(uint8 lchip, uint8 type, uint16 dport, uint32* p_value)
{
    uint8  mii_idx    = 0;
    uint8  pcs_idx    = 0;
    uint8  core_id    = 0;
    uint8  port_type  = 0;
    uint32 value[2]   = {0};
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedMii0Status_dbgMiiRxFaultType0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, mii_idx, 2, fld_info));
        value[0] = fld_info[0].value;
        value[1] = fld_info[1].value;

        *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedPcsXfi0Status_badBerCnt0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedPcsXfi0Status_hiBer0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_xfi_status(lchip, core_id, 0, pcs_idx, 2, fld_info));
        value[0] = fld_info[0].value;

        *p_value = value[0];
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, pcs_idx, 1, fld_info));
        value[0] = fld_info[0].value;

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_xlg_link_status(uint8 lchip, uint8 type, uint16 dport, uint32* p_value)
{
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint32 value[4]     = {0};
    uint32 value_sub[4] = {0};
    reg_field_info_t fld_info[8]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedMii0Status_dbgMiiRxFaultType0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, 0, 2, fld_info));
        value[0] = fld_info[0].value;
        value[1] = fld_info[1].value;

        *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        sal_memset(fld_info, 0xff, 8 * sizeof(reg_field_info_t));
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedPcsXlgStatus_bipErrCnt0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedPcsXlgStatus_bipErrCnt1_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 2, 0, SharedPcsXlgStatus_bipErrCnt2_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 3, 0, SharedPcsXlgStatus_bipErrCnt3_f);
        /*SET_REG_SOURCE_FIELD_INFO(fld_info + 4, 0, SharedPcsXfi0Status_errBlockCnt0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 5, 0, SharedPcsXfi0Status_errBlockCnt1_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 6, 0, SharedPcsXfi0Status_errBlockCnt2_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 7, 0, SharedPcsXfi0Status_errBlockCnt3_f);*/

        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_xlg_status(lchip, core_id, 0, 8, fld_info));
        value[0] = fld_info[0].value;
        value[1] = fld_info[1].value;
        value[2] = fld_info[2].value;
        value[3] = fld_info[3].value;
        /*value_sub[0] = fld_info[4].value;
        value_sub[1] = fld_info[5].value;
        value_sub[2] = fld_info[6].value;
        value_sub[3] = fld_info[7].value;*/

        *p_value = (value[0]+value[1]+value[2]+value[3]+value_sub[0]+value_sub[1]+ value_sub[2]+value_sub[3]);
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, 0, 1, fld_info));
        value[0] = fld_info[0].value;

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_lg_link_status(uint8 lchip, uint8 type, uint16 dport, uint32* p_value)
{
    uint8  step         = 0;
    uint8  mii_idx      = 0;
    uint8  pcs_idx      = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint32 cmd          = 0;
    uint32 tb_id        = 0;
    uint32 tb_id_sub    = 0;
    uint32 field_id     = 0;
    uint32 value[4]     = {0};
    uint32 value_sub[4] = {0};
    reg_field_info_t fld_info[8]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};
    SharedPcsXfi1Status_m share_pcs_status;

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,  core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,     port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,       mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,       pcs_idx);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;

    }

    if((pcs_idx != 0) && (pcs_idx != 2))
    {
        return CTC_E_INVALID_PARAM;
    }
#if 0
    if (port_attr->pcs_reset_en == 1)
    {
        if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
        {
            *p_value = TRUE;
        }
        
        if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
        {
            *p_value = FALSE;
        }

        return CTC_E_NONE;
    }
#endif
    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedMii0Status_dbgMiiRxFaultType0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, mii_idx, 2, fld_info));
        value[0] = fld_info[0].value;
        value[1] = fld_info[1].value;

        *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        /*First Lg use xlg status, second Lg use lg status*/
        if (pcs_idx == 0)
        {
            tb_id    = SharedPcsXlgStatus_t;
            field_id = SharedPcsXlgStatus_bipErrCnt0_f;
        }
        else
        {
            tb_id    = SharedPcsLgStatus_t;
            field_id = SharedPcsLgStatus_lgPcs1BipErrCnt0_f;
        }
        step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
        tb_id_sub = SharedPcsXfi0Status_t + pcs_idx;

        cmd    = DRV_IOR(tb_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &share_pcs_status));

        DRV_IOR_FIELD(lchip, tb_id, field_id, &value[0], &share_pcs_status);
        DRV_IOR_FIELD(lchip, tb_id, field_id + 1, &value[1], &share_pcs_status);
        DRV_IOR_FIELD(lchip, tb_id, field_id + 2, &value[2], &share_pcs_status);
        DRV_IOR_FIELD(lchip, tb_id, field_id + 3, &value[3], &share_pcs_status);

        cmd    = DRV_IOR(tb_id_sub, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &share_pcs_status));
        DRV_IOR_FIELD(lchip, tb_id_sub, SharedPcsXfi0Status_errBlockCnt0_f, &value_sub[0], &share_pcs_status);

        cmd    = DRV_IOR(tb_id_sub+step, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &share_pcs_status));
        DRV_IOR_FIELD(lchip, tb_id_sub+step, SharedPcsXfi0Status_errBlockCnt0_f, &value_sub[1], &share_pcs_status);

        cmd    = DRV_IOR(tb_id_sub+step*2, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &share_pcs_status));
        DRV_IOR_FIELD(lchip, tb_id_sub+step*2, SharedPcsXfi0Status_errBlockCnt0_f, &value_sub[2], &share_pcs_status);

        cmd    = DRV_IOR(tb_id_sub+step*3, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &share_pcs_status));
        DRV_IOR_FIELD(lchip, tb_id_sub+step*3, SharedPcsXfi0Status_errBlockCnt0_f, &value_sub[3], &share_pcs_status);

        *p_value = (value[0]+value[1]+value[2]+value[3]+value_sub[0]+value_sub[1]+ value_sub[2]+value_sub[3]);
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, mii_idx, 1, fld_info));
        value[0] = fld_info[0].value;

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_cg_link_status(uint8 lchip, uint8 type, uint16 dport, uint32* p_value)
{
    uint8  core_id   = 0;
    uint8  port_type = 0;
    uint32 value[4]  = {0};
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }
#if 0
    if (port_attr->pcs_reset_en == 1)
    {
        if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
        {
            *p_value = TRUE;
        }
        
        if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
        {
            *p_value = FALSE;
        }

        return CTC_E_NONE;
    }
#endif
    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedMii0Status_dbgMiiRxFaultType0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, 0, 2, fld_info));
        value[0] = fld_info[0].value;
        value[1] = fld_info[1].value;

        *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_xfi_status(lchip, core_id, 0, 0, 1, fld_info));
        value[0] = fld_info[0].value;
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_xfi_status(lchip, core_id, 0, 1, 1, fld_info));
        value[1] = fld_info[0].value;
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_xfi_status(lchip, core_id, 0, 2, 1, fld_info));
        value[2] = fld_info[0].value;
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_xfi_status(lchip, core_id, 0, 3, 1, fld_info));
        value[3] = fld_info[0].value;

        *p_value += (value[0]+value[1]+ value[2]+value[3]);
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, 0, 1, fld_info));
        value[0] = fld_info[0].value;

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}


int32
_sys_at_cpumac_get_link_up(uint8 lchip, uint16 dport, uint32* p_is_up, uint32 is_phy_link, uint8 mii_link_type)
{
    /*uint32 unidir_en = 0;*/
    uint8  type      = 0;
    uint8  if_mode   = 0;
    uint8  port_type = 0;
    /*uint32 remote_link = 1;
    uint32 auto_neg_en = 0;
    uint32 auto_neg_mode = 0;*/
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_is_up);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,     if_mode);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Port %d is not used \n", dport);
        return CTC_E_INVALID_CONFIG;
    }

    if(SYS_AT_IS_MODE_NONE(if_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Port %d is none mode \n", dport);
        return CTC_E_INVALID_CONFIG;
    }

    /*CTC_ERROR_RETURN(_sys_at_mac_get_cl37_auto_neg(lchip, dport, CTC_PORT_PROP_AUTO_NEG_EN, &auto_neg_en));
    CTC_ERROR_RETURN(_sys_at_mac_get_cl37_auto_neg(lchip, dport, CTC_PORT_PROP_AUTO_NEG_MODE, &auto_neg_mode));
    CTC_ERROR_RETURN_(_sys_at_mac_get_unidir_en(lchip, dport, &unidir_en));*/

    type = (SYS_MAC_MII_LINK_FM == mii_link_type) ? SYS_PORT_MAC_STATUS_TYPE_LINK :
            ((SYS_MAC_MII_LINK_RAW == mii_link_type) ? SYS_PORT_MAC_STATUS_TYPE_LINK_RAW : SYS_PORT_MAC_STATUS_TYPE_CODE_ERR);

    switch (if_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_get_sgmii_link_status(lchip, type, dport, p_is_up));
            /*if (is_phy_link && auto_neg_en)
            {
                CTC_ERROR_RETURN(_sys_tmm_cpumac_get_cl37_an_remote_status(lchip, gport, auto_neg_mode, 
                                                 NULL, &remote_link));
                if (FALSE == remote_link)
                {
                    *p_is_up = FALSE;
                }
            }*/
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
        case CTC_CHIP_SERDES_XFI_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_get_xfi_xxvg_link_status(lchip, type, dport, p_is_up));
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_get_xlg_link_status(lchip, type, dport, p_is_up));
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_get_lg_link_status(lchip, type, dport, p_is_up));
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            CTC_ERROR_RETURN(_sys_at_cpumac_get_cg_link_status(lchip, type, dport, p_is_up));
            break;
        default:
            break;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_link_up(uint8 lchip, uint16 dport, uint32 is_phy_link, uint8 mii_link_type, uint32* p_is_up)
{
    uint8  port_type = 0;
    uint16 mac_id    = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,                mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_get_link_up(lchip, dport, p_is_up, is_phy_link, mii_link_type));
    }
    else if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mac_get_mii_link_status(lchip, mac_id, mii_link_type, p_is_up));
    }
    else
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_STATUS, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

        /* SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% dport %u is not used \n", dport); */
        return CTC_E_INVALID_PORT;
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_get_link_up(uint8 lchip, uint16 lport, uint32* p_is_up, uint32 is_phy_link)
{
    uint16 dport = DMPS_INVALID_VALUE_U16;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    CTC_PTR_VALID_CHECK(p_is_up);
    SYS_MAC_INIT_CHECK();

    if(is_phy_link && (CTC_E_NONE == sys_usw_phy_get_phy_register_exist(lchip, lport)))
    {
        CTC_ERROR_RETURN(sys_usw_phy_get_phy_property(lchip, lport, CTC_PORT_PROP_LINK_UP, (void*)p_is_up));
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, is_phy_link, SYS_MAC_MII_LINK_FM, p_is_up));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_STATUS, (*p_is_up));
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_fec(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  fec_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,              dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE, fec_type);

    *p_value = fec_type;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_speed(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  speed_mode   = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);

    *p_value = speed_mode;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_fec_cnt_base_addr(uint8 lchip, uint8 mac_group_id, uint8 mac_idx, 
                                             uint32* p_base_addr, uint32* p_sne_addr, uint32* p_sel_addr)
{
    uint32 base_addr = 0; /*McPcs400RxFecErrChanMon*/
    uint32 sne_addr  = 0; /*McPcs400RxFecErrChan0Mon*/
    uint32 sel_addr  = 0; /*McPcs400RxFecErrLaneMon*/
    /* get mac_group_id 0-4 address */
    if (mac_group_id < 5)
    {
        if (mac_idx < 4)
        {
            base_addr = 0x800c4380 + mac_group_id * 0x100000;
            sne_addr  = 0x800c4400 + mac_group_id * 0x100000;
            sel_addr  = 0x800c4600 + mac_group_id * 0x100000;
        }
        else
        {
            base_addr = 0x800c4b80 + mac_group_id * 0x100000;
            sne_addr  = 0x800c4c00 + mac_group_id * 0x100000;
            sel_addr  = 0x800c4e00 + mac_group_id * 0x100000;
        }
    }
    /* get mac_group_id 5-9 address */
    else if (mac_group_id < 10)
    {
        if (mac_idx < 4)
        {
            base_addr = 0x808c4380 + (mac_group_id - 5) * 0x100000;
            sne_addr  = 0x808c4400 + (mac_group_id - 5) * 0x100000;
            sel_addr  = 0x808c4600 + (mac_group_id - 5) * 0x100000;
        }
        else
        {
            base_addr = 0x808c4b80 + (mac_group_id - 5) * 0x100000;
            sne_addr  = 0x808c4c00 + (mac_group_id - 5) * 0x100000;
            sel_addr  = 0x808c4e00 + (mac_group_id - 5) * 0x100000;
        }
    }
    /* get mac_group_id 10-14 address */
    else if (mac_group_id < 15)
    {
        if (mac_idx < 4)
        {
            base_addr = 0x814c4380 - (mac_group_id - 10) * 0x100000;
            sne_addr  = 0x814c4400 - (mac_group_id - 10) * 0x100000;
            sel_addr  = 0x814c4600 - (mac_group_id - 10) * 0x100000;
        }
        else
        {
            base_addr = 0x814c4380 - (mac_group_id - 10) * 0x100000;
            sne_addr  = 0x814c4c00 - (mac_group_id - 10) * 0x100000;
            sel_addr  = 0x814c4e00 - (mac_group_id - 10) * 0x100000;
        }
    }
    /* get mac_group_id 15-19 address */
    else if (mac_group_id < 20)
    {
        if (mac_idx < 4)
        {
            base_addr = 0x81cc4380 - (mac_group_id - 15) * 0x100000;
            sne_addr  = 0x81cc4400 - (mac_group_id - 15) * 0x100000;
            sel_addr  = 0x81cc4600 - (mac_group_id - 15) * 0x100000;
        }
        else
        {
            base_addr = 0x81cc4b80 - (mac_group_id - 15) * 0x100000;
            sne_addr  = 0x81cc4c00 - (mac_group_id - 15) * 0x100000;
            sel_addr  = 0x81cc4e00 - (mac_group_id - 15) * 0x100000;
        }
    }
    else
    {
        SYS_USW_VALID_PTR_WRITE(p_base_addr, DMPS_INVALID_VALUE_U32);
        SYS_USW_VALID_PTR_WRITE(p_sne_addr,  DMPS_INVALID_VALUE_U32);
        SYS_USW_VALID_PTR_WRITE(p_sel_addr,  DMPS_INVALID_VALUE_U32);
        return CTC_E_INVALID_PARAM;
    }

    SYS_USW_VALID_PTR_WRITE(p_base_addr, base_addr);
    SYS_USW_VALID_PTR_WRITE(p_sne_addr,  sne_addr);
    SYS_USW_VALID_PTR_WRITE(p_sel_addr,  sel_addr);
    return CTC_E_NONE;
}

void
_sys_at_mac_self_check_fec_cnt_print(ctc_port_fec_cnt_t* fec_cnt, uint32 fec_type)
{
    uint8 item;
    uint8 dup = FALSE;
    uint32 sect = 0;

    if (SYS_DMPS_FEC_TYPE_FC2112 == fec_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "FEC Symbol error count - PCSL           : -\n");
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "FEC Symbol error count - total          : -\n");
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "FEC Symbol error count - PCSL           : ");
        for(item = 0; item < CTC_PORT_FEC_MAX_PCSL_NUM; item++)
        {
            SYS_CONDITION_CONTINUE(0 == fec_cnt->pcsl_sym_err_cnt[item]);
            if(dup)
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n                                          ");
            }
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "L[%u] %u", item, fec_cnt->pcsl_sym_err_cnt[item]);
            dup = TRUE;

            sect += fec_cnt->pcsl_sym_err_cnt[item];
        }
        if(!dup)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0");
        }
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-40s: %u\n", "FEC Symbol error count - total", sect);
    }

    dup = FALSE;
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-40s: %u\n", "FEC CW count of total", fec_cnt->sym_err_cnt[0]);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-40s: %u\n", "FEC CW count of corrected Error", fec_cnt->correct_cnt);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-40s: %u\n", "FEC CW count of uncorrected Error", fec_cnt->uncorrect_cnt);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "FEC CW count of symbol error 1~15       : ");
    for(item = 1; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
    {
        SYS_CONDITION_CONTINUE(0 == fec_cnt->sym_err_cnt[item]);
        if(dup)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n                                          ");
        }
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "SE%u %u", item, fec_cnt->sym_err_cnt[item]);
        dup = TRUE;
    }
    if(!dup)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0");
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
}

int32 
_sys_at_mac_get_fec_cnt(uint8 lchip, uint16 dport, void* p_value)
{
    uint8  cnt           = 0;
    uint8  mac_group_id  = 0;
    uint8  core_id       = 0;
    uint8  mac_idx       = 0;
    uint8  port_type     = 0;
    uint16 if_mode       = 0;
    uint32 cmd           = 0;
    uint32 fld_id[2]     = {0,0};
    uint32 tbl_id        = 0;
    uint32 step          = 0;
    uint32 correct_cnt   = 0;
    uint32 uncorrect_cnt = 0;
    uint32 index         = 0;
    uint32 fec_val       = 0;
    uint32 value_c       = 0;
    uint32 value_uc      = 0;
    uint32 value_sne     = 0;
    uint32 value_sel     = 0;
    uint32 addr_c        = 0;
    uint32 addr_uc       = 0;
    uint32 addr_sne      = 0;
    uint32 addr_sel      = 0;
    uint32 base_addr     = 0;
    uint32 sneb_addr     = 0;
    uint32 selb_addr     = 0;
    uint8  item          = 0;
    uint8  pcsl_num      = 0;
    uint8  i             = 0;
    uint8  max_i         = 0;
    uint32 sen_cw_cnt[CTC_PORT_FEC_CW_SYM_ERR_NUM] = {0};
    uint32 symb_err_pcsl[CTC_PORT_FEC_MAX_PCSL_NUM] = {0};
    RsFec0StatusSharedFec_m cpumacrsstats;
    XgFec1StatusSharedFec_m cpumacfcstats;
    ctc_port_fec_cnt_t*     fec_cnt   = (ctc_port_fec_cnt_t*)p_value;
    sys_dmps_db_upt_info_t  port_info = {0};

    SYS_CONDITION_RETURN(!fec_cnt, CTC_E_INVALID_PTR);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "dport:0x%04X\n", dport);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_FEC_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX, mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE, fec_val);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE, port_type);

    if(SYS_DMPS_FEC_TYPE_NONE == fec_val)    /*FEC : None*/
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " dport %d FEC is not enable.\n",dport);
        return CTC_E_INVALID_PARAM;
    }

    if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        if((SYS_DMPS_FEC_TYPE_RS528 == fec_val) || (SYS_DMPS_FEC_TYPE_RS544 == fec_val))
        {
            step      = RsFec1StatusSharedFec_t - RsFec0StatusSharedFec_t;
            tbl_id    = RsFec0StatusSharedFec_t + mac_idx * step;
            fld_id[0] = RsFec0StatusSharedFec_dbgRsFec0UnCoCwCount_f;
            fld_id[1] = RsFec0StatusSharedFec_dbgRsFec0CorrCwCount_f;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumacrsstats));
            DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &uncorrect_cnt, &cpumacrsstats);
            DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &correct_cnt, &cpumacrsstats);
        }          
        else
        {
            if(CTC_CHIP_SERDES_XLG_MODE == if_mode)
            {
                step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
                for(tbl_id = XgFec0StatusSharedFec_t; tbl_id <= XgFec6StatusSharedFec_t; tbl_id += step)
                {
                    fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                    fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumacfcstats));
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &value_uc, &cpumacfcstats);
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &value_c, &cpumacfcstats);
                    uncorrect_cnt += value_uc;
                    correct_cnt   += value_c;
                }
            }
            else if(CTC_CHIP_SERDES_LG_MODE == if_mode)
            {
                step = XgFec1StatusSharedFec_t - XgFec0StatusSharedFec_t;
                if(2 <= mac_idx)
                {           
                    for(tbl_id = XgFec4StatusSharedFec_t; tbl_id <= XgFec7StatusSharedFec_t; tbl_id += step)
                    {
                        fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                        fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumacfcstats));
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &value_uc, &cpumacfcstats);
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &value_c, &cpumacfcstats);
                        uncorrect_cnt += value_uc;
                        correct_cnt   += value_c;
                    }
                }
                else
                {
                    for(tbl_id = XgFec0StatusSharedFec_t; tbl_id <= XgFec3StatusSharedFec_t; tbl_id += step)
                    {
                        fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                        fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumacfcstats));
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &value_uc, &cpumacfcstats);
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &value_c, &cpumacfcstats);
                        uncorrect_cnt += value_uc;
                        correct_cnt   += value_c;
                    }
                }
            }
            else
            {               
                step      = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
                tbl_id    = XgFec0StatusSharedFec_t + mac_idx * step;
                fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumacfcstats));
                DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &uncorrect_cnt, &cpumacfcstats);
                DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &correct_cnt, &cpumacfcstats);
            }
        }
    }
    else
    {
        SYS_AT_GET_PCSL_NUM_BY_MODE(if_mode, pcsl_num);
        SYS_CONDITION_RETURN(CTC_PORT_FEC_MAX_PCSL_NUM < pcsl_num, CTC_E_INVALID_PARAM);
        switch (if_mode)
        {
            case CTC_CHIP_SERDES_XFI_MODE:
            case CTC_CHIP_SERDES_XLG_MODE:
            case CTC_CHIP_SERDES_XLG_R1_MODE:
            case CTC_CHIP_SERDES_XLG_R2_MODE:
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_LG_MODE:
            case CTC_CHIP_SERDES_LG_R1_MODE:
            case CTC_CHIP_SERDES_CG_MODE:
            case CTC_CHIP_SERDES_CG_R2_MODE:
                CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt_base_addr(lchip, mac_group_id, mac_idx, 
                    &base_addr, &sneb_addr, &selb_addr));
                if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) && (CTC_CHIP_SERDES_LG_MODE == if_mode))
                {
                    max_i = 2;
                }
                else if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) && (CTC_CHIP_SERDES_XLG_MODE == if_mode))
                {
                    max_i = 4;
                }
                else
                {
                    max_i = 1;
                }
                for(i = 0; i < max_i; i++)
                {
                    addr_c  = base_addr + (1 + 6 * ((mac_idx+i) % 4)) * 4;
                    addr_uc = base_addr + (2 + 6 * ((mac_idx+i) % 4)) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                    correct_cnt += value_c;
                    uncorrect_cnt += value_uc;

                    for(item = 0; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
                    {
                        addr_sne = sneb_addr + (4 * item) + 0x40 * ((mac_idx+i) % 4 * 2);
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                        sen_cw_cnt[item] += value_sne;
                    }

                    for(item = 0; item < pcsl_num; item++)
                    {
                        addr_sel = selb_addr + (((mac_idx+i) % 4 * 4) + item) * 4;
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sel, &value_sel));
                        symb_err_pcsl[item] += value_sel;
                    }
                }
                break;
            case CTC_CHIP_SERDES_CG_R1_MODE:
                if ((SYS_DMPS_FEC_TYPE_RS544INT != fec_val) && (SYS_DMPS_FEC_TYPE_RS272INT != fec_val))
                {
                    CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt_base_addr(lchip, mac_group_id, mac_idx, 
                        &base_addr, &sneb_addr, &selb_addr));
                    addr_c  = base_addr + (1 + 6 * (mac_idx % 4)) * 4;
                    addr_uc = base_addr + (2 + 6 * (mac_idx % 4)) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                    correct_cnt   = value_c;
                    uncorrect_cnt = value_uc;

                    for(item = 0; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
                    {
                        addr_sne = sneb_addr + (4 * item) + 0x40 * (mac_idx % 4 * 2);
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                        sen_cw_cnt[item] += value_sne;
                    }
                }
                else
                {
                    CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt_base_addr(lchip, mac_group_id, mac_idx, 
                        &base_addr, &sneb_addr, &selb_addr));
                    for (cnt = 0; cnt < 2; cnt++)
                    {
                        addr_c  = base_addr + (1 + 6 * (mac_idx % 4) + 3 * cnt) * 4;
                        addr_uc = base_addr + (2 + 6 * (mac_idx % 4) + 3 * cnt) * 4;
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                        correct_cnt   += value_c;
                        uncorrect_cnt += value_uc;

                        for(item = 0; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
                        {
                            addr_sne = sneb_addr + (4 * item) + 0x40 * (mac_idx % 4 * 2 + cnt);
                            CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                            sen_cw_cnt[item] += value_sne;
                        }
                    }
                }

                for(item = 0; item < pcsl_num; item++)
                {
                    addr_sel = selb_addr + ((mac_idx % 4 * 4) + item) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sel, &value_sel));
                    symb_err_pcsl[item] += value_sel;
                }
                break;
            case CTC_CHIP_SERDES_CCG_R2_MODE:
                CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt_base_addr(lchip, mac_group_id, mac_idx, 
                    &base_addr, &sneb_addr, &selb_addr));
                for (cnt = 0; cnt < 2; cnt++)
                {
                    addr_c  = base_addr + (1 + 6 * (mac_idx % 4) + 6 * cnt) * 4;
                    addr_uc = base_addr + (2 + 6 * (mac_idx % 4) + 6 * cnt) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                    correct_cnt   += value_c;
                    uncorrect_cnt += value_uc;

                    for(item = 0; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
                    {
                        addr_sne = sneb_addr + (4 * item) + 0x40 * (mac_idx % 4 * 2 + cnt * 2);
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                        sen_cw_cnt[item] += value_sne;
                    }
                }

                for(item = 0; item < pcsl_num; item++)
                {
                    addr_sel = selb_addr + ((mac_idx % 4 * 4) + item) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sel, &value_sel));
                    symb_err_pcsl[item] += value_sel;
                }
                break;
            case CTC_CHIP_SERDES_CCG_R4_MODE:
            case CTC_CHIP_SERDES_CDG_R4_MODE:
            case CTC_CHIP_SERDES_CDG_R8_MODE:
                CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt_base_addr(lchip, mac_group_id, mac_idx, 
                    &base_addr, &sneb_addr, &selb_addr));
                for (cnt = 0; cnt < 2; cnt++)
                {
                    addr_c  = base_addr + (1 + 12 * cnt) * 4;
                    addr_uc = base_addr + (2 + 12 * cnt) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                    correct_cnt   += value_c;
                    uncorrect_cnt += value_uc;

                    for(item = 0; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
                    {
                        addr_sne = sneb_addr + (4 * item) + 0x40 * (mac_idx % 4 * 2 + cnt * 4);
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                        sen_cw_cnt[item] += value_sne;
                    }
                }

                for(item = 0; item < pcsl_num; item++)
                {
                    addr_sel = selb_addr + item * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sel, &value_sel));
                    symb_err_pcsl[item] += value_sel;
                }
                break;
            case CTC_CHIP_SERDES_DCCCG_R8_MODE:
                CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt_base_addr(lchip, mac_group_id, mac_idx, 
                    &base_addr, &sneb_addr, &selb_addr));
                for (cnt = 0; cnt < 2; cnt++)
                {
                    addr_c  = base_addr + (1 + 12 * cnt) * 4;
                    addr_uc = base_addr + (2 + 12 * cnt) * 4;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                    correct_cnt   += value_c;
                    uncorrect_cnt += value_uc;

                    addr_c  += 0x800;
                    addr_uc += 0x800;
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &value_c));
                    CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &value_uc));
                    correct_cnt   += value_c;
                    uncorrect_cnt += value_uc;

                    for(item = 0; item < CTC_PORT_FEC_CW_SYM_ERR_NUM; item++)
                    {
                        addr_sne = sneb_addr + (4 * item) + 0x40 * (mac_idx % 4 * 2 + cnt * 4);
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                        sen_cw_cnt[item] += value_sne;

                        addr_sne += 0x800;
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sne, &value_sne));
                        sen_cw_cnt[item] += value_sne;
                    }

                    for(item = 0; item < (pcsl_num/2); item++)
                    {
                        addr_sel = selb_addr + item * 4 + 0x800 * cnt;
                        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_sel, &value_sel));
                        symb_err_pcsl[cnt*(pcsl_num/2) + item] += value_sel;
                    }
                }
                break;
            default:
                break;
        }
    }

    fec_cnt->correct_cnt   = correct_cnt;
    fec_cnt->uncorrect_cnt = uncorrect_cnt;
    sal_memcpy(fec_cnt->sym_err_cnt,    sen_cw_cnt,    CTC_PORT_FEC_CW_SYM_ERR_NUM * sizeof(uint32));
    sal_memcpy(fec_cnt->pcsl_sym_err_cnt, symb_err_pcsl, CTC_PORT_FEC_MAX_PCSL_NUM * sizeof(uint32));

    return  CTC_E_NONE;
}

int32 
_sys_at_mac_get_serdes_auto_neg_local_ability(uint8 lchip, uint16 psd, sys_datapath_an_ability_t* p_ability)
{
    uint8  core_id  = SYS_AT_GET_CORE_ID_BY_SERDES(psd);
    uint16 dport    = 0;
    uint32 index    = 0;
    uint32 inst_id  = SYS_AT_GET_PSD_SC(psd);
    uint32 cmd      = 0;
    AnethAdvAbility_m ability_reg;

    if (CTC_E_NONE != sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PSD, psd, DMPS_DB_TYPE_PORT, NULL, &dport))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% [%s@%d] Feature not support \n", __FUNCTION__, __LINE__);
        return CTC_E_NOT_SUPPORT;
    }

    index = DRV_INS(inst_id, 0);
    cmd   = DRV_IOR(AnethAdvAbility_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ability_reg));

    DRV_IOR_FIELD(lchip, AnethAdvAbility_t, AnethAdvAbility_cfgAdvAbility_f, &p_ability->base_ability0, &ability_reg);
    DRV_IOR_FIELD(lchip, AnethAdvAbility_t, AnethAdvAbility_cfgNextPageTx0_f, &p_ability->np0_ability0, &ability_reg);
    DRV_IOR_FIELD(lchip, AnethAdvAbility_t, AnethAdvAbility_cfgNextPageTx1_f, &p_ability->np1_ability0, &ability_reg);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"serdes_id",     psd);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n",__FUNCTION__, "base_ability0", p_ability->base_ability0);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"base_ability1", p_ability->base_ability1);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np0_ability0",  p_ability->np0_ability0);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np0_ability1",  p_ability->np0_ability1);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np1_ability0",  p_ability->np1_ability0);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np1_ability1",  p_ability->np1_ability1);
    
    return CTC_E_NONE;
}

int32
_sys_at_mac_get_serdes_auto_neg_remote_ability(uint8 lchip, uint16 psd, sys_datapath_an_ability_t* p_ability)
{
    uint8  core_id  = SYS_AT_GET_CORE_ID_BY_SERDES(psd);
    uint32 index    = 0;
    uint32 inst_id  = SYS_AT_GET_PSD_SC(psd);
    uint32 cmd      = 0;
    AnethNegAbility_m ability_reg;


    index = DRV_INS(inst_id, 0);
    cmd   = DRV_IOR(AnethNegAbility_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ability_reg));

    DRV_IOR_FIELD(lchip, AnethNegAbility_t, AnethNegAbility_monLpAdvAbility_f, &p_ability->base_ability0, &ability_reg);
    DRV_IOR_FIELD(lchip, AnethNegAbility_t, AnethNegAbility_monLpNextPage0_f, &p_ability->np0_ability0, &ability_reg);
    DRV_IOR_FIELD(lchip, AnethNegAbility_t, AnethNegAbility_monLpNextPage1_f, &p_ability->np1_ability0, &ability_reg);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"serdes_id",     psd);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n",__FUNCTION__, "base_ability0", p_ability->base_ability0);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"base_ability1", p_ability->base_ability1);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np0_ability0",  p_ability->np0_ability0);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np0_ability1",  p_ability->np0_ability1);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np1_ability0",  p_ability->np1_ability0);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " [%s] %-32s : 0x%08x\n", __FUNCTION__,"np1_ability1",  p_ability->np1_ability1);

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl73_autoneg_ability(uint8 lchip, uint16 dport, uint32 type, sys_datapath_an_ability_t* p_ability)
{
    uint8  cnt        = 0;
    uint8  serdes_num = 0;
    uint8  port_type  = 0;
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};
    sys_dmps_db_upt_info_t port_info              = {0};
    sys_datapath_an_ability_t serdes_ability[DMPS_MAX_NUM_PER_MODULE];

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d\n", dport);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                 dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);

    if (!SYS_USW_IS_NETWORK_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% dport %d is not used \n", dport);
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));

    /* if auto_neg_ok, should get ability */
    if (type)
    {
        for(cnt = 0; cnt < serdes_num; cnt++)
        {
            CTC_ERROR_RETURN(_sys_at_mac_get_serdes_auto_neg_remote_ability(lchip, physic_serdes[cnt], serdes_ability + cnt));
        }
    }
    else
    {
        for(cnt = 0; cnt < serdes_num; cnt++)
        {
            CTC_ERROR_RETURN(_sys_at_mac_get_serdes_auto_neg_local_ability(lchip, physic_serdes[cnt], serdes_ability + cnt));
        }
    }
    sal_memset(p_ability, 0, sizeof(sys_datapath_an_ability_t));
    for(cnt = 0; cnt < serdes_num; cnt++)
    {
        p_ability->base_ability0 |= serdes_ability[cnt].base_ability0;
        p_ability->base_ability1 |= serdes_ability[cnt].base_ability1;
        p_ability->np0_ability0 |= serdes_ability[cnt].np0_ability0;
        p_ability->np0_ability1 |= serdes_ability[cnt].np0_ability1;
        p_ability->np1_ability0 |= serdes_ability[cnt].np1_ability0;
        p_ability->np1_ability1 |= serdes_ability[cnt].np1_ability1;
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,
        "port %s base ability: 0x%08x %08x, next page0: 0x%08x %08x, next page1: 0x%08x %08x\n",
        type?"remote":"local", p_ability->base_ability0, p_ability->base_ability1, p_ability->np0_ability0,
        p_ability->np0_ability1, p_ability->np1_ability0, p_ability->np1_ability1);

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl73_ability(uint8 lchip, uint16 dport, uint32 type, void* p_ability)
{
    uint32* ability = NULL;
    sys_datapath_an_ability_t cl73_ability = {0};

    SYS_MAC_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_ability);

    ability = (uint32*) p_ability;

    CTC_ERROR_RETURN(_sys_at_mac_get_cl73_autoneg_ability(lchip, dport, type, &cl73_ability));
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_10GBASE_KR)
    {
        *ability |= (CTC_PORT_CL73_10GBASE_KR);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_40GBASE_KR4)
    {
        *ability |= (CTC_PORT_CL73_40GBASE_KR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_40GBASE_CR4)
    {
        *ability |= (CTC_PORT_CL73_40GBASE_CR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_100GBASE_KR4)
    {
        *ability |= (CTC_PORT_CL73_100GBASE_KR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_100GBASE_CR4)
    {
        *ability |= (CTC_PORT_CL73_100GBASE_CR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_25GBASE_KR_S)
    {
        *ability |= (CTC_PORT_CL73_25GBASE_KRS);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_25GBASE_KR)
    {
        *ability |= (CTC_PORT_CL73_25GBASE_KR);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_50GBASE_KR)
    {
        *ability |= (CTC_PORT_CL73_50GBASE_KR);
        *ability |= (CTC_PORT_CL73_50GBASE_CR);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_100GBASE_KR2)
    {
        *ability |= (CTC_PORT_CL73_100GBASE_KR2);
        *ability |= (CTC_PORT_CL73_100GBASE_CR2);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_200GBASE_KR4)
    {
        *ability |= (CTC_PORT_CL73_200GBASE_KR4);
        *ability |= (CTC_PORT_CL73_200GBASE_CR4);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_25G_RS_FEC_REQ)
    {
        *ability |= (CTC_PORT_CL73_25G_RS_FEC_REQUESTED);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_25G_BASER_FEC_REQ)
    {
        *ability |= (CTC_PORT_CL73_25G_BASER_FEC_REQUESTED);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_FEC_SUP)
    {
        *ability |= (CTC_PORT_CL73_FEC_ABILITY);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_FEC_REQ)
    {
        *ability |= (CTC_PORT_CL73_FEC_REQUESTED);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_25GBASE_KR1)
    {
        *ability |= (CTC_PORT_CSTM_25GBASE_KR1);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_25GBASE_CR1)
    {
        *ability |= (CTC_PORT_CSTM_25GBASE_CR1);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_50GBASE_KR2)
    {
        *ability |= (CTC_PORT_CSTM_50GBASE_KR2);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_50GBASE_CR2)
    {
        *ability |= (CTC_PORT_CSTM_50GBASE_CR2);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_400GBASE_CR8)
    {
        *ability |= (CTC_PORT_CSTM_400GBASE_CR8);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL91_FEC_SUP)
    {
        *ability |= (CTC_PORT_CSTM_RS_FEC_ABILITY);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL74_FEC_SUP)
    {
        *ability |= (CTC_PORT_CSTM_BASER_FEC_ABILITY);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL91_FEC_REQ)
    {
        *ability |= (CTC_PORT_CSTM_RS_FEC_REQUESTED);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL74_FEC_REQ)
    {
        *ability |= (CTC_PORT_CSTM_BASER_FEC_REQUESTED);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LF1_50GR1)
    {
        *ability |= (CTC_PORT_CSTM_LF1_50GR1);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LF2_100GR2)
    {
        *ability |= (CTC_PORT_CSTM_LF2_100GR2);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LF3_200GR4)
    {
        *ability |= (CTC_PORT_CSTM_LF3_200GR4);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LL_RS_FEC_REQ)
    {
        *ability |= (CTC_PORT_CSTM_LL_RS_FEC_REQ);
    }
    /*ctc_port_cl73_ability_ext_t*/
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_100GBASE_KR1)
    {
        *(ability+1) |= (CTC_PORT_CL73_100GBASE_KR1);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_100GBASE_CR1)
    {
        *(ability+1) |= (CTC_PORT_CL73_100GBASE_CR1);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_200GBASE_KR2)
    {
        *(ability+1) |= (CTC_PORT_CL73_200GBASE_KR2);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_200GBASE_CR2)
    {
        *(ability+1) |= (CTC_PORT_CL73_200GBASE_CR2);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_400GBASE_KR4)
    {
        *(ability+1) |= (CTC_PORT_CL73_400GBASE_KR4);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_400GBASE_CR4)
    {
        *(ability+1) |= (CTC_PORT_CL73_400GBASE_CR4);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_100G_RS_FEC_INT_REQ)
    {
        *(ability+1) |= (CTC_PORT_CL73_100G_RS_FEC_INT_REQUESTED);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_800GETC_KR8)
    {
        *(ability+1) |= (CTC_PORT_CSTM_800G_ETC_KR8);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_800GETC_CR8)
    {
        *(ability+1) |= (CTC_PORT_CSTM_800G_ETC_CR8);
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_signal_detect(uint8 lchip, void* p_psd, uint8* p_sigdet)
{
    uint8 sigdet = 1;
    uint8 sd_lane = 0;
    uint8 idx;
    sys_usw_dmps_serdes_id_t* psd = (sys_usw_dmps_serdes_id_t*)p_psd;

    for(idx = 0; idx < psd->num; idx++)
    {
        CTC_ERROR_RETURN(_sys_at_serdes_get_signal_detect(lchip, psd->serdes[idx], &sd_lane, NULL));
        if(0 == sd_lane)
        {
            sigdet = 0;
            break;
        }
    }
    *p_sigdet = sigdet;

    return CTC_E_NONE;
}

/*
RX_NO_SIGNAL: at least 1 lane sigdet = 0
RX_INVALID_SIGNAL: at least 1 lane CDR = 0, and all lane sigdet = 1
RX_VALID_SIGNAL: all lane CDR = 1
*/
int32
_sys_at_mac_get_signal_valid(uint8 lchip, void* p_psd, uint8* p_sig_vld)
{
    uint8  sig_vld  = RX_VALID_SIGNAL;
    uint8  sd_lane  = 0;
    uint32 cdr_lane = 0;
    uint32 dtl_lane = 0;
    uint8  idx;
    sys_usw_dmps_serdes_id_t* psd = (sys_usw_dmps_serdes_id_t*)p_psd;

    for(idx = 0; idx < psd->num; idx++)
    {
        CTC_ERROR_RETURN(_sys_at_serdes_get_signal_detect(lchip, psd->serdes[idx], &sd_lane, NULL));
        if(0 != sd_lane)
        {
            CTC_ERROR_RETURN(_sys_at_serdes_get_cdr_lock(lchip, psd->serdes[idx], &cdr_lane));
            if(0 != cdr_lane)
            {
                CTC_ERROR_RETURN(_sys_at_serdes_get_dtl_clamp(lchip, psd->serdes[idx], &dtl_lane));
                if(0 != dtl_lane)
                {
                    sig_vld = RX_INVALID_SIGNAL;
                    /*break;*/
                }
            }
            else
            {
                sig_vld = RX_INVALID_SIGNAL;
                /*break;*/
            }
        }
        else
        {
            sig_vld = RX_NO_SIGNAL;
            break;
        }
    }
    *p_sig_vld = sig_vld;

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_port_rx_train_en(uint8 lchip, void* p_psd, uint8 en)
{
    uint8 idx;
    uint16 enable = (0 == en) ? 0 : 1;
    sys_at_serdes_dev_t dev = {0};
    sys_usw_dmps_serdes_id_t* psd = (sys_usw_dmps_serdes_id_t*)p_psd;

    dev.lchip = lchip;
    dev.type = _sys_at_datapath_get_serdes_type(psd->serdes[0]);
    for(idx = 0; idx < psd->num; idx++)
    {
        dev.serdes_id = psd->serdes[idx];
        CTC_ERROR_RETURN(_sys_at_serdes_set_rx_train_en(&dev, enable));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_port_rx_train_stat(uint8 lchip, void* p_psd, uint8* p_stat)
{
    uint8  idx;
    uint32 en_lane = 0;
    uint32 co_lane = 0;
    uint32 fa_lane = 0;
    uint32 en = 1;
    uint32 co = 1;
    uint32 fa = 0;
    sys_at_serdes_dev_t dev = {0};
    sys_usw_dmps_serdes_id_t* psd = (sys_usw_dmps_serdes_id_t*)p_psd;

    dev.lchip = lchip;
    dev.type = _sys_at_datapath_get_serdes_type(psd->serdes[0]);
    for(idx = 0; idx < psd->num; idx++)
    {
        dev.serdes_id = psd->serdes[idx];
        CTC_ERROR_RETURN(_sys_at_serdes_get_rx_train_en(&dev, &en_lane, &co_lane, &fa_lane));
        if(0 == en_lane)
        {
            en = 0;
        }
        if(0 == co_lane)
        {
            co = 0;
        }
        if(1 == fa_lane)
        {
            fa = 1;
        }
    }

    if(0 == en)
    {
        *p_stat = RX_TRAIN_STOP;
    }
    else if(0 == co)
    {
        *p_stat = RX_TRAIN_RUN;
    }
    else if(0 == fa)
    {
        *p_stat = RX_TRAIN_SUCCESS;
    }
    else
    {
        *p_stat = RX_TRAIN_FAIL;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_link_intr(uint8 lchip, uint16 dport, uint32* enable)
{
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint32 index        = 0;
    uint32 cmd          = 0;
    uint32 tbl_id       = 0;
    uint32 value[5]     = {0};
    uint32 tb_value[5]  = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        mac_group_id = 0;
        tbl_id       = CpuMacProcInterruptFunc_t;
        CTC_BIT_SET(value[3], 30 - mac_idx);
        if (3 == mac_idx)
        {
            CTC_BIT_SET(value[3], 31);
        }
        else
        {
            CTC_BIT_SET(value[4], 2 - mac_idx);
        }
    }
    else
    {
        tbl_id       = CtcMacCtlInterruptFunc_t;
        CTC_BIT_SET(value[0], 2 + mac_idx);
        CTC_BIT_SET(value[0], 10 + mac_idx);
    }

    index = DRV_INS(mac_group_id, 2);
    cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, tb_value));

    if(CTC_FLAG_ISSET(tb_value[0], value[0])
        && CTC_FLAG_ISSET(tb_value[3], value[3])
        && CTC_FLAG_ISSET(tb_value[4], value[4]))
    {
        *enable = 0;
    }
    else
    {
        *enable = 1;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl37_auto_neg(uint8 lchip, uint16 dport, uint32 type, uint32* p_value)
{
    uint8  pcs_idx   = 0;
    uint8  if_mode   = 0;
    uint8  core_id   = 0;
    uint8  port_type = 0;
    uint32 value     = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    if (!SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Only CPUMAC port support CL37 AN \n");
        return CTC_E_INVALID_CONFIG;
    }

    if ((CTC_CHIP_SERDES_SGMII_MODE == if_mode)
        || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode)
        || (CTC_CHIP_SERDES_QSGMII_MODE == if_mode))
    {
        if(CTC_PORT_PROP_AUTO_NEG_EN == type)
        {
            if((CTC_CHIP_SERDES_SGMII_MODE == if_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
            {
                SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Cfg_anEnable0_f);
                CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, 1, &fld_info));
                value = fld_info.value;
            }
        }
        else if(CTC_PORT_PROP_AUTO_NEG_MODE == type)
        {
            if((CTC_CHIP_SERDES_SGMII_MODE == if_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
            {
                SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Cfg_anegMode0_f);
                CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, 1, &fld_info));
                value = fld_info.value;
            }
            /* CPUMAC inherit from tsingma  1000Base-X(2'b00), SGMII-Slaver(2'b10) */
            if(0 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_1000BASE_X;
            }
            else if (2 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER;
            }
        }
        else if (CTC_PORT_PROP_AUTO_NEG_FEC == type)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FEC not supported\n");
            return CTC_E_INVALID_PARAM;
        }
    }

    SYS_USW_VALID_PTR_WRITE(p_value, value);

    return CTC_E_NONE;
}

int32
_sys_at_cpumac_get_preamble(uint8 lchip, uint16 dport, uint32 *value)
{
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint8  mii_idx      = 0;
    uint32 val_u32      = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mii_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    SYS_CONDITION_RETURN(!SYS_USW_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PORT);

    SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Cfg_cfgMiiTxPreambleLen0_f);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, mii_idx, 1, &fld_info));
    val_u32 = fld_info.value;

    SYS_USW_VALID_PTR_WRITE(value, val_u32);

    return CTC_E_NONE; 
}


int32
_sys_at_mcmac_get_frame_property(uint8 lchip, uint16 dport, ctc_port_property_t port_prop, uint32* p_value)
{
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  port_type    = 0;
    uint32 value        = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    SYS_CONDITION_RETURN(SYS_DMPS_NETWORK_PORT != port_type, CTC_E_INVALID_PORT);

    switch(port_prop)
    {
        case CTC_PORT_PROP_PADING_EN:
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPadEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_tx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
            value = fld_info.value;
            break;                          
        case CTC_PORT_PROP_PREAMBLE:
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPreambleLen_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_tx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
            value = fld_info.value;
            break;
        case CTC_PORT_PROP_CHK_CRC_EN:
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxCrcCheckEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_rx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
            value = fld_info.value;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxStripCrcEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_tx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
            value = fld_info.value;
             break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxAppendCrcEn_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_tx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
            value = fld_info.value;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
        default:
            return CTC_E_INVALID_PARAM;
    }

    SYS_USW_VALID_PTR_WRITE(p_value, value);

    return CTC_E_NONE;  
}

int32
_sys_at_cpumac_get_frame_property(uint8 lchip, uint16 dport, ctc_port_property_t port_prop, uint32 *p_value)
{
    uint8  core_id             = 0;
    uint8  sgmac_idx           = 0;
    uint8  cfg_index           = 0;
    uint8  port_type           = 0;
    uint16 step                = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 value               = 0;
    uint32 index               = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    Sgmac0TxCfg_m              sgmac_cfg;
    uint32 sgmac_prop_en_cfg_mapping[][2] = {
        /*Tbl                         Field              */
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxCrcChkEn_f},     /*0 : CTC_PORT_PROP_CHK_CRC_EN*/
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxTodAppendEn_f},  /*1 : CTC_PORT_PROP_APPEND_TOD_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxPadEn_f},        /*2 : CTC_PORT_PROP_PADING_EN*/   
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxStripCrcEn_f},   /*3 : CTC_PORT_PROP_STRIP_CRC_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxAppendCrcEn_f},  /*4 : CTC_PORT_PROP_APPEND_CRC_EN*/
    };

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      sgmac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    SYS_CONDITION_RETURN(!SYS_USW_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PORT);

    switch (port_prop)
    {
        case CTC_PORT_PROP_PREAMBLE:
            CTC_ERROR_RETURN(_sys_at_cpumac_get_preamble(lchip, dport, p_value));
            return CTC_E_NONE;
        case CTC_PORT_PROP_CHK_CRC_EN:
            cfg_index = 0;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            cfg_index = 1;
            break;  
        case CTC_PORT_PROP_PADING_EN:
            cfg_index = 2;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
            cfg_index = 3;
            break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
            cfg_index = 4;
            break;
         default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
    }

    step = ((cfg_index >= 2) ? (Sgmac1TxCfg_t - Sgmac0TxCfg_t) : (Sgmac1RxCfg_t - Sgmac0RxCfg_t));
    tbl_id = sgmac_prop_en_cfg_mapping[cfg_index][0] + sgmac_idx * step;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &sgmac_cfg));
    DRV_IOR_FIELD(lchip, tbl_id, sgmac_prop_en_cfg_mapping[cfg_index][1], &value, &sgmac_cfg);

    SYS_USW_VALID_PTR_WRITE(p_value, value);

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_frame_property(uint8 lchip, uint16 dport, ctc_port_property_t port_prop, uint32 *p_value)
{
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "dport:0x%04X, property:%d\n", dport, port_prop);
    /*Sanity check*/
    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_get_frame_property(lchip, dport, port_prop, p_value));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_get_frame_property(lchip, dport, port_prop, p_value));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
        return CTC_E_INVALID_PORT;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_unidir_en(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  unidir_en = 0;
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,               dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_UNIDIR_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,      port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_UNIDIR_EN, unidir_en);

    SYS_CONDITION_RETURN(!SYS_USW_IS_NETWORK_PORT(port_type), CTC_E_INVALID_PORT);

    SYS_USW_VALID_PTR_WRITE(p_value, unidir_en);

    return CTC_E_NONE;
}

int32
_sys_at_mcmac_get_ipg(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  mac_group_id = 0;
    uint8  port_type = 0;
    uint8  mac_idx   = 0;
    uint8  core_id   = 0;
    uint32 value     = 0;
    uint32 cfg_en    = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    SYS_CONDITION_RETURN(SYS_DMPS_NETWORK_PORT != port_type, CTC_E_INVALID_PORT);

    SET_REG_SOURCE_FIELD_INFO(fld_info,     mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgLen_f);
    SET_REG_SOURCE_FIELD_INFO(fld_info + 1, mac_idx, McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxCtSuperG2Mod_f);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_tx_cfg(lchip, core_id, mac_group_id, 2, fld_info));
    value  = fld_info[0].value;
    cfg_en = fld_info[1].value;

    SYS_USW_VALID_PTR_WRITE(p_value, ((cfg_en << 8) | value));

    return CTC_E_NONE; 
}

int32
_sys_at_cpumac_get_ipg(uint8 lchip, uint16 dport, uint32* value)
{
    uint8  mac_idx   = 0;
    uint8  core_id   = 0;
    uint8  port_type = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    SYS_CONDITION_RETURN(!SYS_USW_IS_CPUMAC_PORT(port_type), CTC_E_INVALID_PORT);

    SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Cfg_cfgMiiTxIpgLen0_f);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, mac_idx, 1, &fld_info));
    *value = fld_info.value;

    return CTC_E_NONE; 
}

int32
_sys_at_mac_get_ipg(uint8 lchip, uint16 dport, uint32 *value)
{
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d\n", dport);

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mcmac_get_ipg(lchip, dport, value));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_get_ipg(lchip, dport, value));
    }
    else
    {
        return CTC_E_INVALID_PORT;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_xpipe_en(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  xpipe_en  = 0;
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,               dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_XPIPE_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,      port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_XPIPE_EN,  xpipe_en);

    SYS_CONDITION_RETURN(!(SYS_DMPS_NETWORK_PORT == (port_type)), CTC_E_INVALID_PORT);

    SYS_USW_VALID_PTR_WRITE(p_value, xpipe_en);

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_tailts_en(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint32 bit1         = 0;
    uint32 bit0         = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    SYS_MAC_INIT_CHECK();
    
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    SYS_CONDITION_RETURN(SYS_DMPS_NETWORK_PORT != port_type, CTC_E_INVALID_PORT);

    SET_REG_SOURCE_FIELD_INFO(fld_info,     mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsEn_f);
    SET_REG_SOURCE_FIELD_INFO(fld_info + 1, mac_idx, McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsMode_f);
    CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mac_rx_cfg(lchip, core_id, mac_group_id, 2, fld_info));
    bit1 = fld_info[0].value;
    bit0 = fld_info[1].value;

    SYS_USW_VALID_PTR_WRITE(p_value, ((bit1 << 1) | bit0));

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_link_fault(uint8 lchip, uint16 dport, uint32 *p_value)
{
    uint8  mac_idx       = 0;
    uint8  mac_group_id  = 0;
    uint8  core_id       = 0;
    uint8  port_type     = 0;
    uint32 value         = 0;
    uint32 fault_bitmap  = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "dport:0x%04X, ", dport);

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);


    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxFaultType_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_debug_stats(lchip, core_id, mac_group_id, 1, &fld_info));
        value = fld_info.value;
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Status_dbgMiiRxFaultType0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0status(lchip, core_id, 0, mac_idx, 1, &fld_info));
        value = fld_info.value;
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Port %d is not used \n", dport);
        return CTC_E_INVALID_PORT;
    }

    fault_bitmap = (value ? (0x0 | (0x1 << (value - 1))) : 0);
    *p_value = (((*p_value) & 0xfffffff8) | (fault_bitmap & 0x00000007));

    return CTC_E_NONE;
}

/*get tx force fault type*/
int32
_sys_at_mac_get_tx_force_fault(uint8 lchip, uint16 dport, uint32* p_fault_bmp)
{
    uint8  mac_idx       = 0;
    uint8  mac_group_id  = 0;
    uint8  core_id       = 0;
    uint8  port_type     = 0;
    uint32 value         = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_cfg(lchip, core_id, mac_group_id, 1, &fld_info));
        value = fld_info.value;
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_type))
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Cfg_cfgMiiRxPCHLen0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, mac_idx, 1, &fld_info));
        value = fld_info.value;
        value = CTC_FLAG_ISSET(value, 0x00000002) ? 1 : 0;
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Port %d is invalid \n", dport);
        return CTC_E_INVALID_PORT;
    }

    *p_fault_bmp &= (~((uint32)CTC_PORT_FAULT_FORCE)); /*clear bit 3*/
    if(0 != value) /*set bit 3*/
    {
        *p_fault_bmp |= CTC_PORT_FAULT_FORCE;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_serdes_info_capability(uint8 lchip, uint16 dport, ctc_port_serdes_info_t* p_value)
{
    uint8  idx        = 0;
    uint8  serdes_num = 0;
    uint8  if_mode    = 0;
    uint16 serdes_id  = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"dport:%d\n", dport);

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, 
        DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));

    if (MCHIP_DMPS(lchip)->psd_to_serdes)
    {
        CTC_ERROR_RETURN(MCHIP_DMPS(lchip)->psd_to_serdes(lchip, physic_serdes[0], &serdes_id));
    }
    else
    {
        serdes_id = physic_serdes[0];
    }

    p_value->serdes_id   = serdes_id;
    p_value->serdes_mode = if_mode;
    p_value->serdes_num  = serdes_num;

    for(idx = 0; idx < p_value->serdes_num; idx++)
    {
        if (MCHIP_DMPS(lchip)->psd_to_serdes)
        {
            CTC_ERROR_RETURN(MCHIP_DMPS(lchip)->psd_to_serdes(lchip, physic_serdes[idx], &serdes_id));
        }
        else
        {
            serdes_id = physic_serdes[idx];
        }

        p_value->serdes_id_array[idx] = serdes_id;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_speed_mode_capability(uint8 lchip, uint16 dport, uint32* speed_mode_bitmap)
{
    uint8  port_type  = 0;
    uint32 tmp_bitmap = 0;
    uint16 logic_serdes_dc = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,      logic_serdes_dc);

    if (SYS_DMPS_NETWORK_PORT == port_type)
    {
        tmp_bitmap |= (1 << CTC_PORT_SPEED_10G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_40G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_100G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_25G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_50G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_200G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_400G);
        if (SYS_AT_SERDES_112G == _sys_at_datapath_get_serdes_type(logic_serdes_dc))
        {
            tmp_bitmap |= (1 << CTC_PORT_SPEED_800G);
        }
    }
    else if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        tmp_bitmap |= (1 << CTC_PORT_SPEED_1G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_2G5);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_10G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_20G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_40G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_100G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_25G);
        tmp_bitmap |= (1 << CTC_PORT_SPEED_50G);
    }

    *speed_mode_bitmap = tmp_bitmap;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_if_type_capability(uint8 lchip, uint16 dport, uint32* if_type_bitmap)
{
    uint8  port_type          = 0;
    uint32 tmp_if_type_bitmap = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_XFI);
    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_KR);
    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_CR);
    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_KR2);
    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_CR2);
    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_KR4);
    tmp_if_type_bitmap |= (1 << CTC_PORT_IF_CR4);

    if (SYS_DMPS_NETWORK_PORT == port_type)
    {
        tmp_if_type_bitmap |= (1 << CTC_PORT_IF_KR8);
        tmp_if_type_bitmap |= (1 << CTC_PORT_IF_CR8);
    }
    else if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        tmp_if_type_bitmap |= (1 << CTC_PORT_IF_SGMII);
        tmp_if_type_bitmap |= (1 << CTC_PORT_IF_2500X);
        tmp_if_type_bitmap |= (1 << CTC_PORT_IF_QSGMII);
    }

    *if_type_bitmap = tmp_if_type_bitmap;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_fec_type_capability(uint8 lchip, uint16 dport, uint32* p_value)
{
    uint8  if_mode  = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    CTC_PTR_VALID_CHECK(p_value);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    switch(if_mode)
    {
        case CTC_CHIP_SERDES_CDG_R8_MODE:
        case CTC_CHIP_SERDES_CCG_R4_MODE:
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:
        case CTC_CHIP_SERDES_CDG_R4_MODE:
        case CTC_CHIP_SERDES_CCG_R2_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS544);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272);
            break;
        case CTC_CHIP_SERDES_CG_R1_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS544);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS544_INT);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272_INT);
            break;
        case CTC_CHIP_SERDES_CG_R2_MODE:
        case CTC_CHIP_SERDES_LG_R1_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS544);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS528);
            break;
        case CTC_CHIP_SERDES_XLG_R1_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS544);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272);
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS528);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_FC2112);
            break;
            
        case CTC_CHIP_SERDES_LG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS528);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS544);
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS528);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS544);
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
        case CTC_CHIP_SERDES_XLG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_FC2112);
            break;
        default:
            *p_value = (1 << CTC_PORT_FEC_TYPE_NONE);
            break;
    }
    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl73_capability(uint8 lchip, uint16 dport, uint32* p_capability)
{
    uint8  if_mode   = 0;
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_PTR_VALID_CHECK(p_capability);
    CTC_PTR_VALID_CHECK(p_capability + 1);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    SYS_CONDITION_RETURN(!SYS_USW_IS_NETWORK_PORT(port_type), CTC_E_INVALID_PORT);

    if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        switch(if_mode)
        {
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
                *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                 CTC_PORT_CL73_25GBASE_KRS |
                                 CTC_PORT_CL73_25GBASE_CRS |
                                 CTC_PORT_CL73_25GBASE_KR |
                                 CTC_PORT_CL73_25GBASE_CR |
                                 CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                 CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                 CTC_PORT_CSTM_25GBASE_KR1 |
                                 CTC_PORT_CSTM_25GBASE_CR1 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED);
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                 CTC_PORT_CSTM_50GBASE_CR2 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED);
                break;
            case CTC_CHIP_SERDES_CG_MODE:
            case CTC_CHIP_SERDES_XLG_MODE:
                *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                 CTC_PORT_CL73_40GBASE_CR4 |
                                 CTC_PORT_CL73_100GBASE_KR4 |
                                 CTC_PORT_CL73_100GBASE_CR4 |
                                 CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED |
                                 CTC_PORT_CL73_25G_BASER_FEC_REQUESTED);
                break;
            default:
                *p_capability = 0;
                break;
        }
    }
    else
    {
        switch(if_mode)
        {
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
            case CTC_CHIP_SERDES_LG_R1_MODE:
            case CTC_CHIP_SERDES_XLG_R1_MODE:
            case CTC_CHIP_SERDES_CG_R1_MODE:
                *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                 CTC_PORT_CL73_25GBASE_KRS |
                                 CTC_PORT_CL73_25GBASE_CRS |
                                 CTC_PORT_CL73_25GBASE_KR |
                                 CTC_PORT_CL73_25GBASE_CR |
                                 CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                 CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                 CTC_PORT_CSTM_25GBASE_KR1 |
                                 CTC_PORT_CSTM_25GBASE_CR1 |
                                 CTC_PORT_CL73_50GBASE_KR |
                                 CTC_PORT_CL73_50GBASE_CR |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED|
                                 CTC_PORT_CSTM_LF1_50GR1|
                                 CTC_PORT_CSTM_LL_RS_FEC_REQ);
                *(p_capability + 1) = (CTC_PORT_CL73_100GBASE_KR1|
                                        CTC_PORT_CL73_100GBASE_CR1|
                                        CTC_PORT_CL73_100G_RS_FEC_INT_REQUESTED);
                break;
            case CTC_CHIP_SERDES_LG_MODE:
            case CTC_CHIP_SERDES_XLG_R2_MODE:
            case CTC_CHIP_SERDES_CG_R2_MODE:
            case CTC_CHIP_SERDES_CCG_R2_MODE:
                *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                 CTC_PORT_CSTM_50GBASE_CR2 |
                                 CTC_PORT_CL73_100GBASE_KR2 |
                                 CTC_PORT_CL73_100GBASE_CR2 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED|
                                 CTC_PORT_CSTM_LF2_100GR2|
                                 CTC_PORT_CSTM_LL_RS_FEC_REQ);
                *(p_capability + 1) = (CTC_PORT_CL73_200GBASE_KR2|
                                        CTC_PORT_CL73_200GBASE_CR2);
                break;
            case CTC_CHIP_SERDES_CG_MODE:
            case CTC_CHIP_SERDES_XLG_MODE:
            case CTC_CHIP_SERDES_CCG_R4_MODE:
            case CTC_CHIP_SERDES_CDG_R4_MODE:
                *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                 CTC_PORT_CL73_40GBASE_CR4 |
                                 CTC_PORT_CL73_100GBASE_KR4 |
                                 CTC_PORT_CL73_100GBASE_CR4 |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED|
                                 CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                 CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                 CTC_PORT_CSTM_LF3_200GR4);
                *(p_capability + 1) = (CTC_PORT_CL73_400GBASE_KR4|
                                        CTC_PORT_CL73_400GBASE_CR4);
                break;
            case CTC_CHIP_SERDES_CDG_R8_MODE:
            case CTC_CHIP_SERDES_DCCCG_R8_MODE:
                *p_capability = (CTC_PORT_CSTM_400GBASE_CR8 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED);
                *(p_capability + 1) = (CTC_PORT_CSTM_800G_ETC_CR8|
                                        CTC_PORT_CSTM_800G_ETC_KR8);
                break;
            default:
                *p_capability = 0;
                break;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl37_flowctl_ability_local(uint8 lchip, uint16 dport, uint32* value)
{
    uint8  core_id    = 0;
    uint8  if_mode    = 0;
    uint8  port_type  = 0;
    uint8  pcs_idx    = 0;
    uint32 val_32     = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);

    if (((CTC_CHIP_SERDES_SGMII_MODE != if_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != if_mode))
        || (!SYS_USW_IS_CPUMAC_PORT(port_type)))
    {
        *value = 0;
        return CTC_E_NONE;
    }

    SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Cfg_localPauseAbility0_f);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(lchip, core_id, 0, pcs_idx, 1, &fld_info));
    val_32 = fld_info.value;

    switch(val_32)
    {
        case SYS_AT_ASMDIR_0_PAUSE_0:
            val_32 = ((!CTC_PORT_PAUSE_ABILITY_TX_EN) & (!CTC_PORT_PAUSE_ABILITY_RX_EN));
            break;
        case SYS_AT_ASMDIR_0_PAUSE_1:
            val_32 = (CTC_PORT_PAUSE_ABILITY_TX_EN | CTC_PORT_PAUSE_ABILITY_RX_EN);
            break;
        case SYS_AT_ASMDIR_1_PAUSE_0:
            val_32 = CTC_PORT_PAUSE_ABILITY_TX_EN;
            break;
        case SYS_AT_ASMDIR_1_PAUSE_1:
        default:
            val_32 = CTC_PORT_PAUSE_ABILITY_RX_EN;
            break;
    }

    *value = val_32;

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_cl37_flowctl_ability_remote(uint8 lchip, uint16 dport, uint32* value)
{
    uint8  core_id    = 0;
    uint8  port_type  = 0;
    uint8  pcs_idx    = 0;
    uint16 if_mode    = 0;
    uint32 val_32     = 0;
    uint32 mask       = 0x3;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);

    if (((CTC_CHIP_SERDES_SGMII_MODE != if_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != if_mode))
        || (!SYS_USW_IS_CPUMAC_PORT(port_type)))
    {
        *value = 0;
        return CTC_E_NONE;
    }

    SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSgmii0Status_anRxRemoteCfg0_f);
    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_status(lchip, core_id, 0, pcs_idx, 1, &fld_info));
    val_32 = fld_info.value;

    /*bit[8:7]*/
    val_32 = (val_32 >> 7) & mask;

    switch(val_32)
    {
        case SYS_AT_ASMDIR_0_PAUSE_0:
            val_32 = ((!CTC_PORT_PAUSE_ABILITY_TX_EN) & (!CTC_PORT_PAUSE_ABILITY_RX_EN));
            break;
        case SYS_AT_ASMDIR_0_PAUSE_1:
            val_32 = (CTC_PORT_PAUSE_ABILITY_TX_EN | CTC_PORT_PAUSE_ABILITY_RX_EN);
            break;
        case SYS_AT_ASMDIR_1_PAUSE_0:
            val_32 = CTC_PORT_PAUSE_ABILITY_TX_EN;
            break;
        case SYS_AT_ASMDIR_1_PAUSE_1:
        default:
            val_32 = CTC_PORT_PAUSE_ABILITY_RX_EN;
            break;
    }

    *value = val_32;

    return CTC_E_NONE;
}

int32
sys_at_mac_set_capability(uint8 lchip, uint16 lport, ctc_port_capability_type_t type, uint32 value)
{
    uint16 dport = 0;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port capability, lport:%u, type:%d value:0x%x!\n", lport, type, value);

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    switch (type)
    {
        case CTC_PORT_CAP_TYPE_LOCAL_PAUSE_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_set_cl37_flowctl_ability(lchip, dport, value));
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_get_capability(uint8 lchip, uint16 lport, ctc_port_capability_type_t type, void* p_value)
{
    uint16 dport  = 0;
    uint16 mac_id = 0;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port capability, lport:%u, type:%d!\n", lport, type);

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    switch(type)
    {
        case CTC_PORT_CAP_TYPE_SERDES_INFO:
            CTC_ERROR_RETURN(_sys_at_mac_get_serdes_info_capability(lchip, dport,
                (ctc_port_serdes_info_t*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_MAC_ID:
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_MAC, &mac_id));
            *(uint32*)p_value = (uint32)mac_id;
            break;
        case CTC_PORT_CAP_TYPE_SPEED_MODE:
            CTC_ERROR_RETURN(_sys_at_mac_get_speed_mode_capability(lchip, dport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_IF_TYPE:
            CTC_ERROR_RETURN(_sys_at_mac_get_if_type_capability(lchip, dport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_FEC_TYPE:
            CTC_ERROR_RETURN(_sys_at_mac_get_fec_type_capability(lchip, dport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_CL73_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_get_cl73_capability(lchip, dport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_CL73_REMOTE_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_get_cl73_ability(lchip, dport, 1, p_value));
            break;
        case CTC_PORT_CAP_TYPE_LOCAL_PAUSE_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_get_cl37_flowctl_ability_local(lchip, dport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_REMOTE_PAUSE_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_get_cl37_flowctl_ability_remote(lchip, dport, (uint32*)p_value));
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}


/**
@brief   Config port's properties
*/
int32
sys_at_mac_set_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value)
{
    uint16 dport  = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    uint8  enable = (value) ? TRUE : FALSE;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property, lport:0x%04X, property:%d, value:%d\n", lport, port_prop, value);

    SYS_CONDITION_RETURN(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport), CTC_E_INVALID_PARAM);

    switch (port_prop)
    {
        case CTC_PORT_PROP_CL73_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_set_cl73_ability(lchip, dport, value));
            break;
        case CTC_PORT_PROP_LINKSCAN_EN:
            if(0 == value)
            {
                CTC_ERROR_RETURN(_sys_usw_dmps_set_daemon_en(lchip, 0));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_usw_dmps_set_daemon_en(lchip, 1));
                CTC_ERROR_RETURN(_sys_usw_dmps_set_daemon_gap_ms(lchip, value));
            }
            break;
        case CTC_PORT_PROP_LINK_INTRRUPT_EN:
            CTC_ERROR_RETURN(_sys_at_mac_set_link_intr(lchip, dport, enable));
            break;
        case CTC_PORT_PROP_UNIDIR_EN:
            CTC_ERROR_RETURN(_sys_at_mac_set_unidir_en(lchip, dport, value));
            break;
        case CTC_PORT_PROP_MAC_TX_IPG:
            CTC_ERROR_RETURN(_sys_at_mac_set_ipg(lchip, dport, value));
            break;
        case CTC_PORT_PROP_PREAMBLE:
        case CTC_PORT_PROP_PADING_EN:
        case CTC_PORT_PROP_CHK_CRC_EN:
        case CTC_PORT_PROP_STRIP_CRC_EN:
        case CTC_PORT_PROP_APPEND_CRC_EN:
        case CTC_PORT_PROP_APPEND_TOD_EN:
            CTC_ERROR_RETURN(_sys_at_mac_set_frame_property(lchip, dport, port_prop, value));
            break;
        case CTC_PORT_PROP_MAC_TS_EN:
            CTC_ERROR_RETURN(_sys_at_mac_set_tailts_en(lchip, dport, value));
            break;
        case CTC_PORT_PROP_PAR_DET_EN:
            CTC_ERROR_RETURN(_sys_at_mac_set_parallel_detect_en(lchip, dport, value));
            break;
        case CTC_PORT_PROP_ERROR_CHECK:
        case CTC_PORT_PROP_RX_PAUSE_TYPE:
        default:
            return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

/**
@brief    Get port's properties according to gport id
*/
int32
sys_at_mac_get_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32* p_value)
{
    uint32 tmp_val = 0;
    uint16 dport  = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    sys_usw_dmps_serdes_id_t psd = {{0}};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port property, lport:0x%04X, property:%d!\n", lport, port_prop);

    SYS_CONDITION_RETURN(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport), CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &(psd.num), psd.serdes));

    switch (port_prop)
    {
        case CTC_PORT_PROP_CL73_ABILITY:
            CTC_ERROR_RETURN(_sys_at_mac_get_cl73_ability(lchip, dport, 0, (void*) p_value));
            break;
        case CTC_PORT_PROP_LINK_INTRRUPT_EN:
            CTC_ERROR_RETURN(_sys_at_mac_get_link_intr(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_PREAMBLE:
        case CTC_PORT_PROP_PADING_EN:
        case CTC_PORT_PROP_CHK_CRC_EN:
        case CTC_PORT_PROP_STRIP_CRC_EN:
        case CTC_PORT_PROP_APPEND_CRC_EN:
        case CTC_PORT_PROP_APPEND_TOD_EN:
            CTC_ERROR_RETURN(_sys_at_mac_get_frame_property(lchip, dport, port_prop, p_value));
            break;
        case CTC_PORT_PROP_LINKSCAN_EN:
            CTC_ERROR_RETURN(_sys_usw_dmps_get_daemon_en(lchip, &tmp_val));
            if(tmp_val)
            {
                CTC_ERROR_RETURN(_sys_usw_dmps_get_daemon_gap_ms(lchip, p_value));
            }
            else
            {
                *p_value = 0;
            }
            break;
        case CTC_PORT_PROP_UNIDIR_EN:
            CTC_ERROR_RETURN(_sys_at_mac_get_unidir_en(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_MAC_TX_IPG:
            CTC_ERROR_RETURN(_sys_at_mac_get_ipg(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_XPIPE_MODE:
            break;
        case CTC_PORT_PROP_MAC_TS_EN:
            CTC_ERROR_RETURN(_sys_at_mac_get_tailts_en(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_PAR_DET_EN:
            CTC_ERROR_RETURN(_sys_at_mac_get_parallel_detect_en(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_FEC_CNT:
            CTC_ERROR_RETURN(_sys_at_mac_get_fec_cnt(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_FAULT:
            CTC_ERROR_RETURN(_sys_at_mac_get_link_fault(lchip, dport, p_value));
            break;
        case CTC_PORT_PROP_SIGNAL_DETECT:
            CTC_ERROR_RETURN(_sys_at_mac_get_signal_detect(lchip, &psd, (uint8*) p_value));
            break;
        case CTC_PORT_PROP_ERROR_CHECK:
        case CTC_PORT_PROP_RX_PAUSE_TYPE:
        default:
            return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}


#define  __AT_MAC_INTR__
int32
_sys_at_mac_isr_m2c_handler(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    int32  ret           = CTC_E_NONE;
    uint32 cmd           = 0;
    uint32 m_intr_ctl[4] = {0x0};
    uint32 inst_id       = mac_group_id;
    uint32 entry_id      = 0;
    uint32 index         = 0;
    uint32 bit           = 0;
    uint32 core_mcu_id   = mac_group_id;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC,  "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "core_id", core_id);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "mac_group_id", mac_group_id);

    M2C_INTR_HW_LOCK(lchip, core_id, core_mcu_id);
    index = DRV_INS(inst_id, entry_id);
    cmd   = DRV_IOR(McpuIntrIntCtl_t, DRV_ENTRY_FLAG);
    ret = DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, m_intr_ctl);
    if (CTC_E_NONE != ret)
    {
        M2C_INTR_HW_UNLOCK(lchip, core_id, core_mcu_id);
        return ret;
    }

    for (bit = 0; bit < 32; bit ++)
    {
        if(CTC_IS_BIT_SET(m_intr_ctl[0], bit))
        {
            sal_sem_give(p_usw_mac_master[lchip]->p_dmps_msg_sem);
        }
    }
    
    /* Clear isr */
    sal_memset(m_intr_ctl, 0xff, sizeof(m_intr_ctl));

    index = DRV_INS(inst_id, entry_id);
    cmd   = DRV_IOW(McpuIntrIntCtl_t, DRV_ENTRY_FLAG);
    ret   = DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, m_intr_ctl);

    M2C_INTR_HW_UNLOCK(lchip, core_id, core_mcu_id);
    return ret;
}

int32
_sys_at_cpumac_isr_m2c_handler(uint8 lchip, uint8 core_id)
{
    int32  ret           = CTC_E_NONE;
    uint32 cmd           = 0;
    uint32 m_intr_ctl[4] = {0x0};
    uint32 inst_id       = AT_MCU_NUM_PER_CORE - 1;
    uint32 entry_id      = 0;
    uint32 index         = 0;
    uint32 bit           = 0;
    uint32 core_mcu_id   = inst_id;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC,  "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "core_id", core_id);

    M2C_INTR_HW_LOCK(lchip, core_id, core_mcu_id);
    index = DRV_INS(inst_id, entry_id);
    cmd   = DRV_IOR(McpuIntrIntCtl_t, DRV_ENTRY_FLAG);
    ret   = DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, m_intr_ctl);
    if (CTC_E_NONE != ret)
    {
        M2C_INTR_HW_UNLOCK(lchip, core_id, core_mcu_id);
        return ret;
    }

    for (bit = 0; bit < 32; bit ++)
    {
        if(CTC_IS_BIT_SET(m_intr_ctl[0], bit))
        {
            sal_sem_give(p_usw_mac_master[lchip]->p_dmps_msg_sem);
        }
    }
    
    /* Clear isr */
    sal_memset(m_intr_ctl, 0xff, sizeof(m_intr_ctl));

    index = DRV_INS(inst_id, entry_id);
    cmd   = DRV_IOW(McpuIntrIntCtl_t, DRV_ENTRY_FLAG);
    ret   = DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, m_intr_ctl);
    M2C_INTR_HW_UNLOCK(lchip, core_id, core_mcu_id);

    return ret;
}

STATIC int32
_sys_at_mac_isr_linkstat_handler(uint8 lchip, uint8 core_id, uint8 mac_group_id, uint32 value[], uint8* p_link_intr, ctc_port_link_status_t* port_link_status)
{
    uint8  mac_idx = 0;
    uint8  cnt     = 0;
    uint16 mac_id  = 0;
    uint16 dport   = 0;
    uint16 lsd     = 0;
    uint8  gchip_id= 0;
    uint16 lport   = 0;
    uint32 gport   = 0;
    sys_dmps_db_upt_info_t port_info    = {0x0};
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);

    if ((0 == value[0]) && (0 == value[1]))
    {
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip_id));
    for (mac_idx = 0; mac_idx < AT_MAC_ID_NUM_PER_MCMAC; mac_idx++)
    {
        if ((!CTC_IS_BIT_SET(value[0], mac_idx)) && (!CTC_IS_BIT_SET(value[1], mac_idx)))
        {
            continue;
        }

        mac_id = (core_id * AT_MCMAC_NUM_PER_CORE + mac_group_id) * AT_MAC_ID_NUM_PER_MCMAC + mac_idx;
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info,      DMPS_DB_MAC_ID,     mac_id);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info,      DMPS_DB_DPORT,      dport);

        if (DMPS_INVALID_VALUE_U16 == dport)
        {
            lsd = mac_id;
            (void) _sys_at_datapath_get_port_chan_by_serdes(lchip, lsd, NULL, &dport);
        }
        lport = sys_usw_dmps_db_get_lport_by_dport(lchip, dport);
        gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip_id, lport);
        port_link_status[cnt].gport = gport;
        cnt ++;
    }

    *p_link_intr = cnt;

    return CTC_E_NONE;
}

STATIC int32
_sys_at_cpumac_isr_linkstat_handler(uint8 lchip, uint8 core_id, uint32 inst_id, uint32 value[], uint8* p_link_intr, ctc_port_link_status_t* port_link_status)
{
    uint8  lane_id    = 0;
    uint8  cnt        = 0;
    uint16 serdes_id  = 0;
    uint16 dport      = 0;
    uint8  gchip_id   = 0;
    uint16 lport      = 0;
    uint32 gport      = 0;
    sys_dmps_db_upt_info_t port_info    = {0x0};
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);
    if ((0 == value[0]) && (0 == value[1]))
    {
        return CTC_E_NONE;
    }
    
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip_id));
    for (lane_id = 0; lane_id < AT_CPUMAC_PER_CORE; lane_id++)
    {
        if ((!CTC_IS_BIT_SET(value[0], lane_id)) && (!CTC_IS_BIT_SET(value[1], lane_id)))
        {
            continue;
        }

        serdes_id = (core_id == 0 ? AT_SERDES_CPUMAC_START_ID_CORE0 : AT_SERDES_CPUMAC_START_ID_CORE1) + lane_id;
        
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info,      DMPS_DB_PHYSIC_SERDES, serdes_id);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info,      DMPS_DB_DPORT,      dport);

        lport = sys_usw_dmps_db_get_lport_by_dport(lchip, dport);
        gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip_id, lport);
        port_link_status[cnt].gport = gport;
        cnt ++;
    }

    *p_link_intr = cnt;

    return CTC_E_NONE;
}

int32
sys_at_mac_isr_event_dispatch(uint8 lchip, uint32 intr, void* p_data, uint8* p_link_intr, ctc_port_link_status_t* port_link_status)
{
    uint8  core_id   = 0;
    uint32 value     = 0;
    uint8  intr_type = 0;
    uint32 field_id  = 0;
    uint32 inst_id   = 0x0;
    uint32 link_value[2] = {0};
    uint32 pp_per_core   = DMPS_PP_NUM_PER_CORE;
    uint32 isr_field[]   =
    {
        CtcMacCtlInterruptFunc_funcIntrMiiRxLinkDown_f,
        CtcMacCtlInterruptFunc_funcIntrMiiRxLinkUp_f,
        CtcMacCtlInterruptFunc_intrToRlmValid_f,
    };
    sys_usw_intr_isr_data_t *p_isr_data = (sys_usw_intr_isr_data_t*)p_data;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "intr",  intr);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "p_isr_data->ins", p_isr_data->ins);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ 0x%08x %08x %08x %08x\n", "status", p_isr_data->status[3], p_isr_data->status[2], p_isr_data->status[1],p_isr_data->status[0]);

    if (0 == pp_per_core)
    {
        return CTC_E_INVALID_CHIP_ID;
    }
    core_id = (lchip - SYS_PP_BASE(lchip)) / pp_per_core;

    inst_id = p_isr_data->ins;

    /* dispatch isr */
    for (intr_type = 0; intr_type < SYS_AT_MAC_ARRAY_SIZE(isr_field); intr_type ++)
    {
        field_id = isr_field[intr_type];
        DRV_IOR_FIELD(lchip, CtcMacCtlInterruptFunc_t, field_id, &value, p_isr_data->status);

        if (0 == value)
        {
            continue;
        }

        switch(field_id)
        {
            case CtcMacCtlInterruptFunc_funcIntrMiiRxLinkDown_f:
                link_value[0] = value;
                break;
            case CtcMacCtlInterruptFunc_funcIntrMiiRxLinkUp_f:
                link_value[1] = value;
                break;
            case CtcMacCtlInterruptFunc_intrToRlmValid_f:
                CTC_ERROR_RETURN(_sys_at_mac_isr_m2c_handler(lchip, core_id, inst_id));
                break;
            default:
                break;
        }

        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "field_id", field_id);
    }

    CTC_ERROR_RETURN(_sys_at_mac_isr_linkstat_handler(lchip, core_id, inst_id, link_value, p_link_intr, port_link_status));

    return CTC_E_NONE;
}

int32
sys_at_cpumac_isr_event_dispatch(uint8 lchip, uint32 intr, void* p_data, uint8* p_link_intr, ctc_port_link_status_t* port_link_status)
{
    uint8  core_id   = 0;
    uint32 value     = 0;
    uint8  intr_type = 0;
    uint32 lane_id   = 0;
    uint32 field_id  = 0;
    uint32 inst_id   = 0;
    uint32 link_value[2] = {0};
    uint32 *p_val_u32 = (uint32*)p_data;
    uint32 pp_per_core = DMPS_PP_NUM_PER_CORE;
    uint32 isr_field[] =
    {
        CpuMacProcInterruptFunc_miiLinkDownInterruptFunc0_f,
        CpuMacProcInterruptFunc_miiLinkDownInterruptFunc1_f,
        CpuMacProcInterruptFunc_miiLinkDownInterruptFunc2_f,
        CpuMacProcInterruptFunc_miiLinkDownInterruptFunc3_f,
        CpuMacProcInterruptFunc_miiLinkUpInterruptFunc0_f,
        CpuMacProcInterruptFunc_miiLinkUpInterruptFunc1_f,        
        CpuMacProcInterruptFunc_miiLinkUpInterruptFunc2_f,        
        CpuMacProcInterruptFunc_miiLinkUpInterruptFunc3_f,
    };

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "intr",  intr);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ 0x%08x %08x %08x %08x %08x\n", "status", p_val_u32[4], p_val_u32[3], p_val_u32[2], p_val_u32[1], p_val_u32[0]);

    if (0 == pp_per_core)
    {
        return CTC_E_INVALID_CHIP_ID;
    }
    core_id = (lchip - SYS_PP_BASE(lchip)) / pp_per_core;

    if (intr == SYS_INTR_FUNC_MISC_EVENT)
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_isr_m2c_handler(lchip, core_id));
        return CTC_E_NONE;
    }

    for (intr_type = 0; intr_type < SYS_AT_MAC_ARRAY_SIZE(isr_field); intr_type ++)
    { 
        field_id = isr_field[intr_type];
        DRV_IOR_FIELD(lchip, CpuMacProcInterruptFunc_t, field_id, &value, p_val_u32);

        if (0 == value)
        {
            continue;
        }
        if (field_id >= CpuMacProcInterruptFunc_miiLinkUpInterruptFunc0_f)
        {
            lane_id = (field_id - CpuMacProcInterruptFunc_miiLinkUpInterruptFunc0_f) % AT_CPUMAC_PER_CORE;
            CTC_BIT_SET(link_value[1], lane_id);
        }
        else
        {
            lane_id = (field_id - CpuMacProcInterruptFunc_miiLinkDownInterruptFunc0_f) % AT_CPUMAC_PER_CORE;
            CTC_BIT_SET(link_value[0], lane_id);
        }
        
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "field_id", field_id);
    }
    CTC_ERROR_RETURN(_sys_at_cpumac_isr_linkstat_handler(lchip, core_id, inst_id, link_value, p_link_intr, port_link_status));

    return CTC_E_NONE;
}

int32
sys_at_anlt_sm_get_mcu_id_by_dport(uint8 lchip, uint16 dport, uint8* p_mcu_id)
{
    uint8  core_id      = 0x0;
    uint8  mac_group_id = 0x0;
    uint8  port_type    = 0x0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if (SYS_DMPS_NETWORK_PORT == port_type) 
    {
        *p_mcu_id = core_id*AT_MCU_NUM_PER_CORE + mac_group_id; 
    }
    else
    {
        *p_mcu_id = core_id*AT_MCU_NUM_PER_CORE + (AT_MCU_NUM_PER_CORE - 1); 
    }
    
    return CTC_E_NONE;
}

int32
sys_at_anlt_sm_reset_mac(uint8 lchip, uint16 dport, uint8 is_reset)
{
    uint8  enable    = is_reset ? FALSE : TRUE;
    uint8  port_type = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "lchip", lchip);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "dport", dport);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "        %-32s @ %d\n", "is_reset", is_reset);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "        %-32s @ %d\n", "mac enable", enable);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
        
    if (!enable)
    {
#ifndef PCS_ONLY
        /* queue drop */
        CTC_ERROR_RETURN(_sys_usw_dmps_set_flush_en(lchip, dport, TRUE));
#endif
    }

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_set_mac_en(lchip, dport, enable));
    }
    else if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_nw_mac_en(lchip, dport, enable));
    }

    if (enable)
    {
#ifndef PCS_ONLY
        /* close queue drop */
        CTC_ERROR_RETURN(_sys_usw_dmps_set_flush_en(lchip, dport, FALSE));
#endif
    }
    
    return CTC_E_NONE;
}

int32
sys_at_anlt_sm_set_fec(uint8 lchip, uint16 dport, uint32 value)
{
    uint16 lport = sys_usw_dmps_db_get_lport_by_dport(lchip, dport);
    sys_port_api_dmps_info_t port_info = {0};

    SYS_CONDITION_RETURN(lport == SYS_DMPS_INVALID_U16, CTC_E_NONE);

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    CTC_ERROR_RETURN(sys_usw_dmps_db_api_get_port_info(lchip, lport, &port_info));

    if (SYS_DMPS_NETWORK_PORT == port_info.port_type)
    {
        /*change serdes line speed*/
        //CTC_ERROR_RETURN(_sys_tmm_mac_set_fec_serdes_speed(lchip, port_attr, type));
        
        /*low corepll fec map clear before config*/
        //_sys_tmm_mac_low_corepll_fec_free(lchip, port_attr);

        /*set fec config*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_fec_type(lchip, lport, value));

        CTC_ERROR_RETURN(_sys_at_mac_set_nw_config_by_mac_id(lchip, port_info.mac_id));

        /*low corepll fec map remap after config*/
        //_sys_tmm_mac_low_corepll_fec_remap(lchip, lport, port_attr);

    }
    else if (SYS_USW_IS_CPUMAC_PORT(port_info.port_type))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_fec_type(lchip, lport, value));
        CTC_ERROR_RETURN(_sys_at_cpumac_set_fec_config(lchip, dport, value));
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

#define  __AT_MAC_INIT__
int32
sys_at_mac_init(uint8 lchip)
{
#ifndef EMULATION_ENV
    uint8  core_num          = 1;
    uint8  mac_group_id      = 0;
    uint8  core_id           = 0;
    uint32 index             = 0;
    uint32 cmd               = 0;
    uint32 tbl_id            = 0;
    uint32 value             = 0;
    uint32 ctcmac_intr_func  = 0x3fffc;
    uint32 cpumac_intr_func[5] = {0, 0, 0, 0xf8000000, 0x7};
    uint32 ctc_hs_intr_normal  = 0xffffffff;
    uint32 mcu_intr_normal     = 0xffffffff;
    RefDivMcMacPulse_m         rf_mac_pulse;
#endif

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* mac config init */
    CTC_ERROR_RETURN(_sys_at_mac_init_mac_config(lchip));

#ifndef EMULATION_ENV
    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        tbl_id = RefDivMcMacPulse_t;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_mac_pulse));
        value  = 0x4c4a00;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgRefDivMcMacHiBerPulse_f,  &value, &rf_mac_pulse);
        value  = 0x3d0900;  // 0x3d09.00 = 100us * 156.25M/1us
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgRefDivMcMacLinkFilterPulse_f,  &value, &rf_mac_pulse);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_mac_pulse));

        /* unmask link up/down interrupt */
        for (mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
        {
            if (!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id))
            {
                continue;
            }

            /*clear link intr*/
            index = DRV_INS(mac_group_id, 1);
            cmd   = DRV_IOW(CtcMacCtlInterruptFunc_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctcmac_intr_func));
            SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CtcMacCtlInterruptFunc 1 funcIntrMiiRxLinkDown 0xff inst %d\n", mac_group_id);
            SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CtcMacCtlInterruptFunc 1 funcIntrMiiRxLinkUp 0xff inst %d\n", mac_group_id);
            /*unmask link intr*/
            index = DRV_INS(mac_group_id, 3);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctcmac_intr_func));
            SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CtcMacCtlInterruptFunc 3 funcIntrMiiRxLinkDown 0xff inst %d\n", mac_group_id);
            SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CtcMacCtlInterruptFunc 3 funcIntrMiiRxLinkUp 0xff inst %d\n", mac_group_id);

            index = DRV_INS(2 *mac_group_id, 1);
            cmd   = DRV_IOW(CtcHsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_intr_normal));
            index = DRV_INS(2 *mac_group_id + 1, 1);
            cmd   = DRV_IOW(CtcHsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_intr_normal));
            index = DRV_INS(2 *mac_group_id, 3);
            cmd   = DRV_IOW(CtcHsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_intr_normal));
            index = DRV_INS(2 *mac_group_id + 1, 3);
            cmd   = DRV_IOW(CtcHsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_intr_normal));

            index = DRV_INS(mac_group_id, 1);
            cmd   = DRV_IOW(McpuInterruptNormal_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intr_normal));
            index = DRV_INS(mac_group_id, 3);
            cmd   = DRV_IOW(McpuInterruptNormal_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intr_normal));
        }

        /* unmask cpumac link up/down interrupt */
        index = DRV_INS(0, 1);
        cmd   = DRV_IOW(CpuMacProcInterruptFunc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, cpumac_intr_func));
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkDownInterruptFunc0 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkDownInterruptFunc1 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkDownInterruptFunc2 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkDownInterruptFunc3 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkUpInterruptFunc0 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkUpInterruptFunc1 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkUpInterruptFunc2 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 1 miiLinkUpInterruptFunc3 1\n");
        index = DRV_INS(0, 3);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, cpumac_intr_func));
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkDownInterruptFunc0 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkDownInterruptFunc1 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkDownInterruptFunc2 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkDownInterruptFunc3 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkUpInterruptFunc0 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkUpInterruptFunc1 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkUpInterruptFunc2 1\n");
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write CpuMacProcInterruptFunc 3 miiLinkUpInterruptFunc3 1\n");

        index = DRV_INS(AT_MCU_NUM_PER_CORE - 1, 1);
        cmd   = DRV_IOW(McpuInterruptNormal_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intr_normal));
        index = DRV_INS(AT_MCU_NUM_PER_CORE - 1, 3);
        cmd   = DRV_IOW(McpuInterruptNormal_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intr_normal));
    }
#endif

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_link_filter(uint8 lchip, uint16 dport, uint8 filter_type, uint32 filter_ms)
{
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint8  fld_num      = 0;
    uint16 mac_group_id = 0;
    uint16 mac_idx      = 0;
    uint32 value        = 0;
    uint32 en           = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    if(25 < filter_ms)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter length %u(ms) not support, max 25ms! dport %u, filter_type %u\n", 
            filter_ms, dport, filter_type);
        return CTC_E_NOT_SUPPORT;
    }

    en    = (0 == filter_ms) ? 0 : 1;
    value = filter_ms * 10; /*TMM pulse is 0.1ms, so timer value enlarge by x10*/

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
        fld_num = 0;

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f,    en);
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterTimer_f, value);
        }
        else if(SYS_MAC_FAULT_FILTER == filter_type)
        {
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f,    en);
            SET_REG_FIELD_INFO(fld_info , fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterTimer_f, value);
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter type %u not support! dport %u, filter_ms %u\n", 
                filter_type, dport, filter_ms);
            return CTC_E_NOT_SUPPORT;
        }

        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_group_id, fld_num, fld_info));
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            sal_memset(fld_info, 0xff, 2 * sizeof(reg_field_info_t));
            fld_num = 0;
            SET_REG_FIELD_INFO(fld_info , fld_num, 0, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    en);
            SET_REG_FIELD_INFO(fld_info , fld_num, 0, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, value);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_write_sharedmii0cfg(lchip, core_id, 0, mac_idx, fld_num, fld_info));
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter type %u not support! dport %u, filter_ms %u\n",
                filter_type, dport, filter_ms);
            return CTC_E_NOT_SUPPORT;
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid dport %u! port_type %u\n", dport, port_type);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_link_filter(uint8 lchip, uint16 dport, uint8 filter_type, uint32* p_filter_ms)
{
    uint8  core_id      = 0;
    uint8  port_type    = 0;
    uint16 mac_group_id = 0;
    uint16 mac_idx      = 0;
    uint32 value        = 0;
    uint32 en           = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);


    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            SET_REG_SOURCE_FIELD_INFO(fld_info, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f);
            SET_REG_SOURCE_FIELD_INFO(fld_info + 1, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterTimer_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_cfg(lchip, core_id, mac_group_id, 2, fld_info));
            en    = fld_info[0].value;
            value = fld_info[1].value;
        }
        else if(SYS_MAC_FAULT_FILTER == filter_type)
        {
            SET_REG_SOURCE_FIELD_INFO(fld_info,     mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f);
            SET_REG_SOURCE_FIELD_INFO(fld_info + 1, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterTimer_f);
            CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_cfg(lchip, core_id, mac_group_id, 2, fld_info));
            en    = fld_info[0].value;
            value = fld_info[1].value;
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter type %u not support! dport %u\n", filter_type, dport);
            return CTC_E_NOT_SUPPORT;
        }
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            SET_REG_SOURCE_FIELD_INFO(fld_info,     0, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f);
            SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f);
            CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, mac_idx, 2, fld_info));
            en    = fld_info[0].value;
            value = fld_info[1].value;
        }
        else
        {
            en    = 0;
            value = 0;
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid dport %u! port_type %u\n", dport, port_type);
        return CTC_E_INVALID_PARAM;
    }

    /*TMM pulse is 0.1ms, do round off to get ms*/
    if((0 == en) || (0 == value))
    {
        SYS_USW_VALID_PTR_WRITE(p_filter_ms, 0);
    }
    else
    {
        SYS_USW_VALID_PTR_WRITE(p_filter_ms, ((value + 5) / 10));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_set_dir_en(uint8 lchip, uint16 dport, uint8 direcion, uint32 enable)
{
    uint8 dir = (CTC_INGRESS == direcion) ? DMPS_RX : DMPS_TX;

    CTC_ERROR_RETURN(_sys_at_mac_set_mac_pkt_en(lchip, dport, dir, enable));

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_dir_en(uint8 lchip, uint16 dport, uint8 direcion, uint32* p_enable)
{
    uint8 dir = (CTC_INGRESS == direcion) ? DMPS_RX : DMPS_TX;

    CTC_ERROR_RETURN(_sys_at_mac_get_mac_pkt_en(lchip, dport, dir, p_enable));

    return CTC_E_NONE;
}

/*set directional property in dmps, moved from sys_usw_port.c*/
int32
sys_at_mac_set_direction_property(uint8 lchip, uint16 lport,
                                    ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32 value)
{
    uint16 dport        = DMPS_INVALID_VALUE_U16;
    uint32 egress_value = value;
    int32  ret          = CTC_E_NONE;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property with direction, lport:%u, property:%d, dir:%d,\
        value:%d\n", lport, port_prop, dir, value);

    //SYS_MAC_INIT_CHECK();
    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION);

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    /*do write*/
    if ((CTC_INGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                value = (value) ? TRUE : FALSE;
                ret = _sys_at_mac_set_dir_en(lchip, dport, CTC_INGRESS, value);
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }

    value = egress_value;

    if ((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                value = (value) ? TRUE : FALSE;
                ret = _sys_at_mac_set_dir_en(lchip, dport, CTC_EGRESS, value);
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }

    CTC_ERROR_RETURN(ret);

    return CTC_E_NONE;
}

/*get directional property in dmps, moved from sys_usw_port.c*/
int32
sys_at_mac_get_direction_property(uint8 lchip, uint16 lport,
                                    ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value)
{
    uint16 dport = DMPS_INVALID_VALUE_U16;
    int32  ret   = CTC_E_NONE;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port property with direction, lport:%u, property:%d, dir:%d\n", 
        lport, port_prop, dir);

    //SYS_MAC_INIT_CHECK();
    //CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION - 1);

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    /*do read, only get value by CTC_INGRESS or CTC_EGRESS, no CTC_BOTH_DIRECTION*/
    if (CTC_INGRESS == dir)
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                ret = _sys_at_mac_get_dir_en(lchip, dport, CTC_INGRESS, p_value);
                break;
            default:
                return CTC_E_INVALID_PARAM;

        }
    }
    else if (CTC_EGRESS == dir)
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                ret = _sys_at_mac_get_dir_en(lchip, dport, CTC_EGRESS, p_value);
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(ret);

    return CTC_E_NONE;
}

int32
sys_at_mac_set_link_info(uint8 lchip, uint16 lport, void* p_value)
{
    uint16 dport               = 0;
    ctc_port_link_info_t*   p_link_info = (ctc_port_link_info_t*)p_value;
    uint32 unidir_en           = p_link_info->unidir_en;
    uint32 fault               = p_link_info->fault;
    uint32 link_filter         = p_link_info->link_filter;
    uint32 fault_filter        = p_link_info->fault_filter;
    uint32 cur_unidir_en       = 0;
    uint32 cur_fault           = 0;
    uint32 cur_link_filter     = 0;
    uint32 cur_fault_filter    = 0;

    if((25 < link_filter) || (25 < fault_filter))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter length %u %u(ms) not support, max 25ms! lport %u\n", 
            link_filter, fault_filter, lport);
        return CTC_E_NOT_SUPPORT;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(_sys_at_mac_get_unidir_en(lchip, dport, &cur_unidir_en));
    if(cur_unidir_en != unidir_en)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_unidir_en(lchip, dport, unidir_en));
    }

    CTC_ERROR_RETURN(_sys_at_mac_get_tx_force_fault(lchip, dport, &cur_fault));
    if(CTC_FLAG_ISSET(fault, CTC_PORT_FAULT_FORCE) != CTC_FLAG_ISSET(cur_fault, CTC_PORT_FAULT_FORCE))
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_tx_force_fault(lchip, dport, fault));
    }

    CTC_ERROR_RETURN(_sys_at_mac_get_link_filter(lchip, dport, SYS_MAC_LINK_FILTER, &cur_link_filter));
    if(cur_link_filter != link_filter)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_link_filter(lchip, dport, SYS_MAC_LINK_FILTER, link_filter));
    }

    CTC_ERROR_RETURN(_sys_at_mac_get_link_filter(lchip, dport, SYS_MAC_FAULT_FILTER, &cur_fault_filter));
    if(cur_fault_filter != fault_filter)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_link_filter(lchip, dport, SYS_MAC_FAULT_FILTER, fault_filter));
    }

    return CTC_E_NONE;
}

/* get serdes status by gport, sigdet | phyready*/
int32
_sys_at_mac_get_port_serdes_stat(uint8 lchip, uint16 lport, uint8 stat_type, uint32* p_stat)
{
    uint8  idx;
    uint8  is_detect = 0;
    uint32 phy_ready = 0;
    uint8  port_type = 0;
    uint16 psd[DMPS_MAX_NUM_PER_MODULE] = {0};
    uint8  num = 0;
    
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_type(lchip, lport, &port_type));

    if(!SYS_USW_IS_NETWORK_PORT(port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %d is not used \n", lport);
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd, &num));

    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < num, CTC_E_INVALID_PARAM);

    switch(stat_type)
    {
        case SYS_MAC_SERDES_SIGDET:
            for(idx = 0; idx < num; idx++)
            {
                CTC_ERROR_RETURN(_sys_at_serdes_get_signal_detect(lchip, psd[idx], &is_detect, NULL));
                SYS_CONDITION_BREAK(0 == is_detect);
            }
            SYS_USW_VALID_PTR_WRITE(p_stat, is_detect);
            break;
        case SYS_MAC_SERDES_READY:
            for(idx = 0; idx < num; idx++)
            {
                CTC_ERROR_RETURN(_sys_at_serdes_get_cdr_lock(lchip, psd[idx], &phy_ready));
                SYS_CONDITION_BREAK(0 == phy_ready);
            }
            SYS_USW_VALID_PTR_WRITE(p_stat, phy_ready);
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

STATIC int32
sys_at_mac_pcs_status_check(uint8 lchip, uint16 dport, sys_pcs_status_t* pcs_status)
{
    uint8  mac_group_id = 0;
    uint8  pcs400_idx   = 0;
    uint8  pcs_idx      = 0;
    uint8  core_id      = 0;
    uint8  if_mode      = 0;
    uint8  port_type    = 0;
    uint8  loop         = 0;
    uint8  serdes_num   = 0;
    uint16 pcs_id       = 0;
    uint32 tbl_id       = 0;
    uint32 fld_id       = 0;
    uint32 cmd          = 0;
    uint32 step         = 0;
    uint32 index        = 0;
    uint32  fec_val      = 0;
    uint16 physic_serdes[DMPS_MAX_NUM_PER_MODULE] = {0};
    uint8  invalid_value = 3;
    sys_dmps_db_upt_info_t port_info = {0};
    reg_field_info_t fld_info[4]     = {{0}};

    SharedPcsSgmii0Status_m SharedPcsSgmii0Status;
    SharedPcsLgStatus_m SharedPcsLgStatus;
    SharedPcsCgStatus_m SharedPcsCgStatus;
    SharedPcsXlgStatus_m SharedPcsXlgStatus;
    SharedPcsXfi0Status_m SharedPcsXfi0Status;
    GlobalStatusSharedFec_m GlobalStatusSharedFec;
    RsFec0StatusSharedFec_m RsFec0StatusSharedFec;
    XgFec0StatusSharedFec_m XgFec0StatusSharedFec;
    McPcs800RxPhyLaneMon_m McPcs800RxPhyLaneMon;

    uint32 pcs_sync       = invalid_value;
    uint32 rsfec_lock     = invalid_value;
    uint32 xgfec_lock     = invalid_value;
    uint32 fec_am_lock    = invalid_value;
    uint32 rx_block_lock  = invalid_value;
    uint32 rx_am_lock     = invalid_value;
    uint32 rx_cwm_lock    = invalid_value;
    uint32 hi_ber         = invalid_value;

    uint32 code_err_cnt   = 0;
    uint32 bip_err_cnt    = SYS_AT_USELESS_ID8;
    uint32 err_blk_cnt    = SYS_AT_USELESS_ID8;
    uint32 bad_ber_cnt    = SYS_AT_USELESS_ID8;


    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PCS_ID,            pcs_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_val));

    pcs400_idx   = ((pcs_id) / 4) % 2;
        
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_link_status(lchip, dport, &pcs_sync));

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {   
        /* rs fec lock */
        if((SYS_DMPS_FEC_TYPE_RS528 == fec_val) && (CTC_CHIP_SERDES_XXVG_MODE == if_mode)) 
        {
            step = RsFec1StatusSharedFec_t - RsFec0StatusSharedFec_t;
            tbl_id = RsFec0StatusSharedFec_t + step * pcs_idx; 
            fld_id = RsFec0StatusSharedFec_dbgRsFec0RxReady_f;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &RsFec0StatusSharedFec));
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rsfec_lock, &RsFec0StatusSharedFec);
        }
        /* fec am lock */
        if((SYS_DMPS_FEC_TYPE_RS528 == fec_val) && (CTC_CHIP_SERDES_XXVG_MODE == if_mode))
        {
            tbl_id = GlobalStatusSharedFec_t;
            step = GlobalStatusSharedFec_dbgSharedFecAmLock1_f - GlobalStatusSharedFec_dbgSharedFecAmLock0_f;
            fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock0_f + pcs_idx * step;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &GlobalStatusSharedFec));
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &fec_am_lock, &GlobalStatusSharedFec);
        }
        else if((CTC_CHIP_SERDES_LG_MODE == if_mode) && (SYS_DMPS_FEC_TYPE_RS528 == fec_val))
        {
            tbl_id = GlobalStatusSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &GlobalStatusSharedFec));
            if(2 <= pcs_idx)
            {
                for(fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock2_f; fld_id <= GlobalStatusSharedFec_dbgSharedFecAmLock3_f; fld_id ++)
                {
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &fec_am_lock, &GlobalStatusSharedFec);
                    if(0 == fec_am_lock)
                    {
                        break;
                    }
                }    
            }
            else
            {
                for(fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock0_f; fld_id <= GlobalStatusSharedFec_dbgSharedFecAmLock1_f; fld_id ++)
                {
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &fec_am_lock, &GlobalStatusSharedFec);
                    if(0 == fec_am_lock)
                    {
                        break;
                    }
                }
            }
        }
        else if((CTC_CHIP_SERDES_CG_MODE == if_mode) && (SYS_DMPS_FEC_TYPE_RS528 == fec_val))
        {
            tbl_id = GlobalStatusSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &GlobalStatusSharedFec));
            for(fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock0_f; fld_id <= GlobalStatusSharedFec_dbgSharedFecAmLock3_f; fld_id ++)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &fec_am_lock, &GlobalStatusSharedFec);
                if(0 == fec_am_lock)
                {
                    break;
                }
            }
        }
        else
        {
            fec_am_lock = SYS_AT_USELESS_ID32;
        }
        
        /* xg fec lock */
        if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) &&
            ((CTC_CHIP_SERDES_XXVG_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XFI_MODE == if_mode)))
        {
            step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
            tbl_id = XgFec0StatusSharedFec_t + step * pcs_idx;
            fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &XgFec0StatusSharedFec));
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &xgfec_lock, &XgFec0StatusSharedFec);
        }
        else if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) && (CTC_CHIP_SERDES_XLG_MODE == if_mode))
        {
            fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;      
            step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
            for(tbl_id = XgFec0StatusSharedFec_t; tbl_id <= XgFec6StatusSharedFec_t; tbl_id += step)
            {
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &XgFec0StatusSharedFec));
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &xgfec_lock, &XgFec0StatusSharedFec);
                if(0 == xgfec_lock)
                {
                    break;
                }
            }
        }
        else if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) && (CTC_CHIP_SERDES_LG_MODE == if_mode))
        {
            if(2 >= pcs_idx)
            {
                fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;
                step = XgFec1StatusSharedFec_t - XgFec0StatusSharedFec_t;
                for(tbl_id = XgFec0StatusSharedFec_t; tbl_id <= XgFec3StatusSharedFec_t; tbl_id += step)
                { 
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &XgFec0StatusSharedFec));
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &xgfec_lock, &XgFec0StatusSharedFec);
                    if(0 == xgfec_lock)
                    {
                        break;
                    }
                }
            }
            else
            {
                fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;
                step = XgFec1StatusSharedFec_t - XgFec0StatusSharedFec_t;
                for(tbl_id = XgFec4StatusSharedFec_t; tbl_id <= XgFec7StatusSharedFec_t; tbl_id += step)
                {
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &XgFec0StatusSharedFec));
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &xgfec_lock, &XgFec0StatusSharedFec);
                    if(0 == xgfec_lock)
                    {
                        break;
                    }
                }
            }    
        }
       
        /* rx_cwm_lock */
        rx_cwm_lock = SYS_AT_USELESS_ID32;
        /* rx block lock && rx_am_lock && err check */
        if(CTC_CHIP_SERDES_SGMII_MODE == if_mode)
        {
            step = SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t;
            tbl_id = SharedPcsSgmii0Status_t + step * pcs_idx;
            fld_id = SharedPcsSgmii0Status_codeErrCnt0_f;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsSgmii0Status));
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &code_err_cnt, &SharedPcsSgmii0Status);
        }
        else if(CTC_CHIP_SERDES_XFI_MODE == if_mode || CTC_CHIP_SERDES_XXVG_MODE == if_mode)
        {
            step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
            tbl_id = SharedPcsXfi0Status_t + step * pcs_idx;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsXfi0Status));
            fld_id = SharedPcsXfi0Status_badBerCnt0_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &bad_ber_cnt, &SharedPcsXfi0Status);
            fld_id = SharedPcsXfi0Status_hiBer0_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &hi_ber, &SharedPcsXfi0Status);
            fld_id = SharedPcsXfi0Status_errBlockCnt0_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &err_blk_cnt, &SharedPcsXfi0Status);

            if(SYS_DMPS_FEC_TYPE_NONE == fec_val)
            {
                fld_id = SharedPcsXfi0Status_rxBlockLock0_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_block_lock, &SharedPcsXfi0Status);
            }
        }
        else if(CTC_CHIP_SERDES_XLG_MODE == if_mode)
        {
            tbl_id = SharedPcsXlgStatus_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsXlgStatus));
            for(loop = 0; loop < 4; loop++)
            {
                step = SharedPcsXlgStatus_bipErrCnt1_f - SharedPcsXlgStatus_bipErrCnt0_f;
                fld_id = SharedPcsXlgStatus_bipErrCnt0_f + step * loop;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &bip_err_cnt, &SharedPcsXlgStatus);
                if(bip_err_cnt)
                {
                    break;
                }
            }

            if(SYS_DMPS_FEC_TYPE_NONE == fec_val)
            {

                fld_id = SharedPcsXfi0Status_rxBlockLock0_f;        
                step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
                for(tbl_id = SharedPcsXfi0Status_t; tbl_id <= SharedPcsXfi3Status_t; tbl_id += step)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsXfi0Status));
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_block_lock, &SharedPcsXfi0Status);
                    if(0 == rx_block_lock)
                    {
                        break;
                    }
                }   
            }

            if((SYS_DMPS_FEC_TYPE_NONE == fec_val) || (SYS_DMPS_FEC_TYPE_FC2112 == fec_val))
            {
                for(fld_id = SharedPcsXlgStatus_rxAmLock0_f; fld_id <= SharedPcsXlgStatus_rxAmLock3_f; fld_id ++)
                {
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_am_lock, &SharedPcsXlgStatus);
                    if(0 == rx_am_lock)
                    {
                        break;
                    }
                }
            }
        }
        else if(CTC_CHIP_SERDES_LG_MODE == if_mode)
        {
            tbl_id = SharedPcsLgStatus_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsLgStatus));
            for(loop = 0; loop < 4; loop++)
            {
                step = SharedPcsLgStatus_lgPcs1BipErrCnt1_f - SharedPcsLgStatus_lgPcs1BipErrCnt0_f;
                fld_id = SharedPcsLgStatus_lgPcs1BipErrCnt0_f + step * loop;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &bip_err_cnt, &SharedPcsLgStatus);
                if(bip_err_cnt)
                {
                    break;
                }
            }

            if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) || (SYS_DMPS_FEC_TYPE_NONE == fec_val)) 
            {
                if(2 >= pcs_idx)
                {
                    tbl_id = SharedPcsXlgStatus_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsXlgStatus));
                    for(fld_id = SharedPcsXlgStatus_rxAmLock0_f; fld_id <= SharedPcsXlgStatus_rxAmLock3_f; fld_id++)
                    {
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_am_lock, &SharedPcsXlgStatus);
                        if(0 == rx_am_lock)
                        {
                            break;
                        }
                    } 
                }
                else
                {
                    for(fld_id = SharedPcsLgStatus_lgPcs1RxAmLock0_f; fld_id <= SharedPcsLgStatus_lgPcs1RxAmLock3_f; fld_id ++)
                    {
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_am_lock, &SharedPcsLgStatus);
                        if(0 == rx_am_lock)
                        {
                            break;
                        }
                    }    
                }
            }
        }
        else if(CTC_CHIP_SERDES_CG_MODE == if_mode)
        {
            tbl_id = SharedPcsCgStatus_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &SharedPcsCgStatus));
            for(loop = 0; loop < 20; loop++)
            {
                step = SharedPcsCgStatus_cgLane1BipErrCnt_f - SharedPcsCgStatus_cgLane0BipErrCnt_f;
                fld_id = SharedPcsCgStatus_cgLane0BipErrCnt_f + step * loop;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &bip_err_cnt, &SharedPcsCgStatus);
                if(bip_err_cnt)
                {
                    break;
                }
            }

            if(SYS_DMPS_FEC_TYPE_NONE == fec_val)
            {
                for(fld_id = SharedPcsCgStatus_cgRxBlockLock0_f; fld_id <= SharedPcsCgStatus_cgRxBlockLock19_f; fld_id ++)
                {
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_block_lock, &SharedPcsLgStatus);
                    if(0 == rx_block_lock)
                    {
                        break;
                    }
                }

                for(fld_id = SharedPcsCgStatus_cgRxAmLock0_f; fld_id <= SharedPcsCgStatus_cgRxAmLock19_f; fld_id ++)
                {
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &rx_am_lock, &SharedPcsCgStatus);
                    if(0 == rx_am_lock)
                    {
                        break;
                    }
                }
            }
        }       
    }
    else if(SYS_USW_IS_NETWORK_PORT(port_type))
    {
        SET_REG_SOURCE_FIELD_INFO(fld_info,     pcs_idx, McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxHiBer_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, pcs_idx, McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxBadBerCnt_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 2, pcs_idx, McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxErrBlockCnt_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_pcs_debug_stats(lchip, core_id, mac_group_id, 3, fld_info));
        hi_ber      = fld_info[0].value;
        bad_ber_cnt = fld_info[1].value;
        err_blk_cnt = fld_info[2].value;

        /*Rx Block lock && RxAmLock && RxCwmLock */
        SET_REG_SOURCE_FIELD_INFO(fld_info,     2 * pcs_idx, McPcs400RxLaneMon_monRxLane_0_monRxBlockLock_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 2 * pcs_idx, McPcs400RxLaneMon_monRxLane_0_monRxAmLock_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 2, 2 * pcs_idx, McPcs400RxLaneMon_monRxLane_0_monRxCwmLock_f);
        SET_REG_SOURCE_FIELD_INFO(fld_info + 3, 2 * pcs_idx, McPcs400RxLaneMon_monRxLane_0_monRxBipErrCnt_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_read_400_rx_lane_mon(lchip, core_id, 2 * mac_group_id + pcs400_idx, 4, fld_info));

        if(((SYS_DMPS_FEC_TYPE_NONE == fec_val) || (SYS_DMPS_FEC_TYPE_FC2112 == fec_val)) &&
            ((CTC_CHIP_SERDES_XXVG_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XFI_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XLG_MODE == if_mode)
            ||(CTC_CHIP_SERDES_LG_MODE == if_mode)
            ||(CTC_CHIP_SERDES_LG_R1_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XLG_R1_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XLG_R2_MODE == if_mode)
            ||(CTC_CHIP_SERDES_CG_MODE == if_mode)
            ||(CTC_CHIP_SERDES_CG_R2_MODE == if_mode)))
        {
            rx_block_lock = fld_info[0].value;
        }
            
       /* if(((SYS_DMPS_FEC_TYPE_NONE == fec_val) || (SYS_DMPS_FEC_TYPE_FC2112 == fec_val)) &&
        ((CTC_CHIP_SERDES_XLG_MODE == if_mode)
        ||(CTC_CHIP_SERDES_LG_MODE == if_mode)
        ||(CTC_CHIP_SERDES_LG_R1_MODE == if_mode)
        ||(CTC_CHIP_SERDES_XLG_R1_MODE == if_mode)
        ||(CTC_CHIP_SERDES_XLG_R2_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CG_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CG_R2_MODE == if_mode)))
        {*/
            rx_am_lock = fld_info[1].value;
       // }
        /*if(((SYS_DMPS_FEC_TYPE_RS528 == fec_val) || (SYS_DMPS_FEC_TYPE_RS544 == fec_val) || (SYS_DMPS_FEC_TYPE_RS272 == fec_val)) &&
        ((CTC_CHIP_SERDES_XXVG_MODE == if_mode)
        ||(CTC_CHIP_SERDES_LG_R1_MODE == if_mode)
        ||(CTC_CHIP_SERDES_LG_MODE == if_mode)
        ||(CTC_CHIP_SERDES_XLG_R1_MODE == if_mode)
        ||(CTC_CHIP_SERDES_XLG_R2_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CG_R1_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CG_R2_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CG_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CCG_R2_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CCG_R4_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CDG_R4_MODE == if_mode)
        ||(CTC_CHIP_SERDES_CDG_R8_MODE == if_mode)
        ||(CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)))
        {*/
            rx_cwm_lock = fld_info[2].value;

#if 0 
            /*TOD : BipErrCnt */
            bip_err_cnt = fld_info[3].value;
#endif 
       // }
        
        /* FcFecLock */
        if((SYS_DMPS_FEC_TYPE_FC2112 == fec_val) &&
            ((CTC_CHIP_SERDES_XFI_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XXVG_MODE == if_mode)
            ||(CTC_CHIP_SERDES_XLG_MODE == if_mode)))
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, physic_serdes));            
            tbl_id = McPcs800RxPhyLaneMon_t;
            index = DRV_INS(mac_group_id, 0);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &McPcs800RxPhyLaneMon));
            for(loop = 0; loop < serdes_num; loop++)
            {
                step = McPcs800RxPhyLaneMon_monRxPhyLane_1_monFcFecRxBlockLock_f - McPcs800RxPhyLaneMon_monRxPhyLane_0_monFcFecRxBlockLock_f;
                fld_id = McPcs800RxPhyLaneMon_monRxPhyLane_0_monFcFecRxBlockLock_f + (physic_serdes[loop] % 8) * step;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &xgfec_lock, &McPcs800RxPhyLaneMon);
                if(0 == xgfec_lock)
                {
                    break;
                }
            }
        }

    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    pcs_status->pcs_sync = pcs_sync;
    pcs_status->hi_ber = hi_ber;
    pcs_status->bad_ber_cnt =  bad_ber_cnt;
    pcs_status->err_blk_cnt =  err_blk_cnt;
    pcs_status->code_err_cnt =  code_err_cnt;
    pcs_status->bip_err_cnt =  bip_err_cnt;
    pcs_status->rx_block_lock =  rx_block_lock;
    pcs_status->rx_am_lock =  rx_am_lock;
    pcs_status->rx_cwm_lock =  rx_cwm_lock;
    pcs_status->fec_am_lock =  fec_am_lock;
    pcs_status->xgfec_lock =  xgfec_lock;
    pcs_status->rsfec_lock =  rsfec_lock;
    
    return CTC_E_NONE;  
}

int32
_sys_at_mac_get_pcs_err_cnt(uint8 lchip, uint16 dport, uint32 err_cnt[])
{
    sys_pcs_status_t   pcs_status = {0};

    CTC_ERROR_RETURN(sys_at_mac_pcs_status_check(lchip, dport, &pcs_status));

    err_cnt[0] = pcs_status.code_err_cnt;

    return CTC_E_NONE;
}

int32
sys_at_mac_get_link_info(uint8 lchip, uint16 lport, void* p_value)
{
    uint16 dport               = 0;
    uint32 is_link_up          = 0;
    uint32 mac_link_status     = 0;
    uint32 pcs_link_status     = 0;
    uint32 unidir_en           = 0;
    uint32 fault               = 0;
    uint32 signal_detect       = 0;
    uint32 serdes_ready        = 0;
    uint32 link_filter         = 0;
    uint32 fault_filter        = 0;
    ctc_port_link_info_t*   p_link_info = (ctc_port_link_info_t*)p_value;

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, 0, SYS_MAC_MII_LINK_FM, &is_link_up));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, 0, SYS_MAC_MII_LINK_RAW, &mac_link_status));
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_link_status(lchip, dport, &pcs_link_status));
    CTC_ERROR_RETURN(_sys_at_mac_get_unidir_en(lchip, dport, &unidir_en));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_fault(lchip, dport, &fault));
    CTC_ERROR_RETURN(_sys_at_mac_get_tx_force_fault(lchip, dport, &fault));
    CTC_ERROR_RETURN(_sys_at_mac_get_port_serdes_stat(lchip, lport, SYS_MAC_SERDES_SIGDET, &signal_detect));
    CTC_ERROR_RETURN(_sys_at_mac_get_port_serdes_stat(lchip, lport, SYS_MAC_SERDES_READY, &serdes_ready));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_filter(lchip, dport, SYS_MAC_LINK_FILTER, &link_filter));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_filter(lchip, dport, SYS_MAC_FAULT_FILTER, &fault_filter));
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_err_cnt(lchip, dport, p_link_info->pcs_err_cnt));

    p_link_info->is_link_up      = (uint8)is_link_up;
    p_link_info->mac_link_status = (uint8)mac_link_status;
    p_link_info->pcs_link_status = (uint8)pcs_link_status;
    p_link_info->unidir_en       = (uint8)unidir_en;
    p_link_info->fault           = (uint8)fault;
    p_link_info->signal_detect   = (uint8)signal_detect;
    p_link_info->serdes_ready    = (uint8)serdes_ready;
    p_link_info->link_filter     = (uint16)link_filter;
    p_link_info->fault_filter    = (uint16)fault_filter;

    return CTC_E_NONE;
}


//#ifdef PCS_ONLY
int32
_sys_at_mac_get_cpumac_stats(uint8 lchip, uint8 core_id, uint8 mac_idx, uint8 entry_offset, uint64* frame, uint64* bytes)
{
    uint32 val0   = 0;
    uint32 val1   = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;
    QuadSgmacStatsRam_m quad_sgmac_stats_ram;

    tbl_id = QuadSgmacStatsRam_t;
    index = DRV_INS(0, mac_idx * 40 + entry_offset);
    cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &quad_sgmac_stats_ram));

    fld_id = QuadSgmacStatsRam_frameCntDataLo_f;
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &quad_sgmac_stats_ram);
    fld_id = QuadSgmacStatsRam_frameCntDataHi_f;
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &quad_sgmac_stats_ram);
    *frame = (((uint64)val1 << 32) | val0);

    fld_id = QuadSgmacStatsRam_byteCntDataLo_f;
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &quad_sgmac_stats_ram);
    fld_id = QuadSgmacStatsRam_byteCntDataHi_f;
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &quad_sgmac_stats_ram);
    *bytes = (((uint64)val1 << 32) | val0);

    return CTC_E_NONE;
}

int32
_sys_at_mac_clear_cpumac_stats(uint8 lchip, uint8 core_id, uint8 mac_idx, uint8 entry_offset)
{
    uint32 val    = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;
    QuadSgmacStatsRam_m quad_sgmac_stats_ram;

    val = 0;

    tbl_id = QuadSgmacStatsRam_t;
    index = DRV_INS(0, mac_idx * 40 + entry_offset);
    cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &quad_sgmac_stats_ram));

    fld_id = QuadSgmacStatsRam_frameCntDataLo_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val, &quad_sgmac_stats_ram);
    fld_id = QuadSgmacStatsRam_frameCntDataHi_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val, &quad_sgmac_stats_ram);

    fld_id = QuadSgmacStatsRam_byteCntDataLo_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val, &quad_sgmac_stats_ram);
    fld_id = QuadSgmacStatsRam_byteCntDataHi_f;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val, &quad_sgmac_stats_ram);

    cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &quad_sgmac_stats_ram));
    return CTC_E_NONE;
}

int32
_sys_at_mac_get_stats(uint8 lchip, uint8 port_num, uint8 core_id, uint16 dport, uint8 mac_group_id,
                        uint8 mac_idx, uint8 entry_offset, uint64* frame, uint64* bytes)
{
    uint8 cnt     = 0;
    uint8 port_type = 0;
    uint32 val0   = 0;
    uint32 val1   = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    McMacStatsRam0_m mcmac_stats_ram0;
    McMacStatsRam1_m mcmac_stats_ram1;

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    *bytes = 0;
    *frame = 0;

    if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_mac_get_cpumac_stats(lchip, core_id, mac_idx, entry_offset, frame, bytes));
        return CTC_E_NONE;
    }

    if (8 == port_num)
    {
        tbl_id = McMacStatsRam0_t;
        for (cnt = 0; cnt < 4; cnt++)
        {
            index = DRV_INS(mac_group_id, cnt * 40 + entry_offset);
            cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram0));

            fld_id = McMacStatsRam0_frameCntDataLo_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram0);
            fld_id = McMacStatsRam0_frameCntDataHi_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram0);
            *frame += (((uint64)val1 << 32) | val0);

            fld_id = McMacStatsRam0_byteCntDataLo_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram0);
            fld_id = McMacStatsRam0_byteCntDataHi_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram0);
            *bytes += (((uint64)val1 << 32) | val0);
        }

        tbl_id = McMacStatsRam1_t;
        for (cnt = 0; cnt < 4; cnt++)
        {
            index = DRV_INS(mac_group_id, cnt * 40 + entry_offset);
            cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram1));

            fld_id = McMacStatsRam1_frameCntDataLo_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram1);
            fld_id = McMacStatsRam1_frameCntDataHi_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram1);
            *frame += (((uint64)val1 << 32) | val0);

            fld_id = McMacStatsRam1_byteCntDataLo_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram1);
            fld_id = McMacStatsRam1_byteCntDataHi_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram1);
            *bytes += (((uint64)val1 << 32) | val0);
        }
    }
    else
    {
        for (cnt = 0; cnt < port_num; cnt++)
        {
            if (4 > mac_idx)
            {
                tbl_id = McMacStatsRam0_t;
                index = DRV_INS(mac_group_id, (mac_idx + cnt) * 40 + entry_offset);
                cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram0));

                fld_id = McMacStatsRam0_frameCntDataLo_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram0);
                fld_id = McMacStatsRam0_frameCntDataHi_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram0);
                *frame += (((uint64)val1 << 32) | val0);

                fld_id = McMacStatsRam0_byteCntDataLo_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram0);
                fld_id = McMacStatsRam0_byteCntDataHi_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram0);
                *bytes += (((uint64)val1 << 32) | val0);
            }
            else
            {
                tbl_id = McMacStatsRam1_t;
                index = DRV_INS(mac_group_id, (mac_idx + cnt - 4) * 40 + entry_offset);
                cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram1));

                fld_id = McMacStatsRam1_frameCntDataLo_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram1);
                fld_id = McMacStatsRam1_frameCntDataHi_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram1);
                *frame += (((uint64)val1 << 32) | val0);

                fld_id = McMacStatsRam1_byteCntDataLo_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val0, &mcmac_stats_ram1);
                fld_id = McMacStatsRam1_byteCntDataHi_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val1, &mcmac_stats_ram1);
                *bytes += (((uint64)val1 << 32) | val0);
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_clear_stats(uint8 lchip, uint8 port_num, uint8 core_id, uint16 dport, uint8 mac_group_id, uint8 mac_idx, uint8 entry_offset)
{
    uint8 cnt     = 0;
    uint8  port_type = 0;
    uint32 val    = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index  = 0;
    uint32 cmd    = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    McMacStatsRam0_m mcmac_stats_ram0;
    McMacStatsRam1_m mcmac_stats_ram1;
    
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if (SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_mac_clear_cpumac_stats(lchip, core_id, mac_idx, entry_offset));
        return CTC_E_NONE;
    }

    val = 0;
    if (8 == port_num)
    {
        tbl_id = McMacStatsRam0_t;
        for (cnt = 0; cnt < 4; cnt++)
        {
            index = DRV_INS(mac_group_id, cnt * 40 + entry_offset);
            cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram0));

            fld_id = McMacStatsRam0_frameCntDataLo_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);
            fld_id = McMacStatsRam0_frameCntDataHi_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);

            fld_id = McMacStatsRam0_byteCntDataLo_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);
            fld_id = McMacStatsRam0_byteCntDataHi_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram0));
        }

        tbl_id = McMacStatsRam1_t;
        for (cnt = 0; cnt < 4; cnt++)
        {
            index = DRV_INS(mac_group_id, cnt * 40 + entry_offset);
            cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram1));

            fld_id = McMacStatsRam1_frameCntDataLo_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);
            fld_id = McMacStatsRam1_frameCntDataHi_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);

            fld_id = McMacStatsRam1_byteCntDataLo_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);
            fld_id = McMacStatsRam1_byteCntDataHi_f;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram1));
        }
    }
    else
    {
        for (cnt = 0; cnt < port_num; cnt++)
        {
            if (4 > mac_idx)
            {
                tbl_id = McMacStatsRam0_t;
                index = DRV_INS(mac_group_id, (mac_idx + cnt) * 40 + entry_offset);
                cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram0));

                fld_id = McMacStatsRam0_frameCntDataLo_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);
                fld_id = McMacStatsRam0_frameCntDataHi_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);

                fld_id = McMacStatsRam0_byteCntDataLo_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);
                fld_id = McMacStatsRam0_byteCntDataHi_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram0);

                cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram0));
            }
            else
            {
                tbl_id = McMacStatsRam1_t;
                index = DRV_INS(mac_group_id, (mac_idx + cnt - 4) * 40 + entry_offset);
                cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram1));

                fld_id = McMacStatsRam1_frameCntDataLo_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);
                fld_id = McMacStatsRam1_frameCntDataHi_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);

                fld_id = McMacStatsRam1_byteCntDataLo_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);
                fld_id = McMacStatsRam1_byteCntDataHi_f;
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, fld_id, &val, &mcmac_stats_ram1);

                cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcmac_stats_ram1));
            }
        }
    }

    return CTC_E_NONE;
}

int32
sys_at_mac_show_stats(uint8 lchip, uint16 lport)
{
    uint8 core_id      = 0;
    uint8 mac_group_id = 0;
    uint8 mac_idx      = 0;
    uint8 port_num     = 0;
    uint8 if_mode      = 0;
    uint16 dport       = 0;
    uint64 bytes       = 0;
    uint64 frame       = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    if ((CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode) || ((CTC_CHIP_SERDES_CDG_R8_MODE == if_mode)))
    {
        port_num = 8;
    }
    else if (CTC_CHIP_SERDES_CDG_R4_MODE == if_mode)
    {
        port_num = 4;
    }
    else if ((CTC_CHIP_SERDES_CCG_R4_MODE == if_mode) || (CTC_CHIP_SERDES_CCG_R2_MODE == if_mode))
    {
        port_num = 2;
    }
    else
    {
        port_num = 1;
    }

    sal_printf("-------------------------------------------------------------------------------------\n");
    sal_printf("%-30s%-35s%-36s\n", "Type", "Frame", "Byte");
    sal_printf("-------------------------------------------------------------------------------------\n");

    /* get rxGoodUcast */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 0, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodUcast", frame, bytes);

    /* get rxGoodMcast */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 1, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodMcast", frame, bytes);

    /* get rxGoodBcast */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 2, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodBcast", frame, bytes);

    /* get rxGoodPauseFrameNor */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 3, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodPauseFrameNor", frame, bytes);

    /* get rxGoodPauseFramePfc */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 4, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodPauseFramePfc", frame, bytes);

    /* get rxGoodCtlFrame */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 5, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodCtlFrame", frame, bytes);

    /* get rxFecError */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 6, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxFcsError", frame, bytes);

    /* get rxMacOverrun */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 7, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxMacOverrun", frame, bytes);

    /* get rxGoodPktLen < 64B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 8, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodPktLen < 64B", frame, bytes);

    /* get rxBadPktLen < 64B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 9, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxBadPktLen < 64B", frame, bytes);

    /* get MTU1 < rxGoodPktLen <= MTU2 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 10, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "MTU1 < rxGoodPktLen <= MTU2", frame, bytes);

    /* get MTU1 < rxBadPktLen <= MTU2 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 11, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "MTU1 < rxBadPktLen <= MTU2", frame, bytes);

    /* get rxGoodPktLen > MTU2 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 12, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxGoodPktLen > MTU2", frame, bytes);

    /* get rxBadPktLen > MTU2 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 13, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxBadPktLen > MTU2", frame, bytes);

    /* get rxPktLen == 64B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 14, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "rxPktLen == 64B", frame, bytes);

    /* get 64B < rxPktLen <= 127B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 15, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "64B < rxPktLen <= 127B", frame, bytes);

    /* get 127B < rxPktLen <= 255B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 16, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "127B < rxPktLen <= 255B", frame, bytes);

    /* get 255B < rxPktLen <= 511B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 17, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "255B < rxPktLen <= 511B", frame, bytes);

    /* get 511B < rxPktLen <= 1023B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 18, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "511B < rxPktLen <= 1023B", frame, bytes);

    /* get 1023B < rxPktLen <= 1518B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 19, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "1023B < rxPktLen <= 1518B", frame, bytes);

    /* get 1518B < rxPktLen <= 2047B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 20, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "1518B < rxPktLen <= 2047B", frame, bytes);

    /* get 2047B < rxPktLen <= MTU1 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 21, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "2047B < rxPktLen <= MTU1", frame, bytes);

    /* get txGoodUcast */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 22, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txGoodUcast", frame, bytes);

    /* get txGoodMcast */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 23, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txGoodMcast", frame, bytes);

    /* get txGoodBcast */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 24, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txGoodBcast", frame, bytes);

    /* get txGoodPauseFrame */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 25, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txGoodPauseFrame", frame, bytes);

    /* get txGoodCtlFrame */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 26, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txGoodCtlFrame", frame, bytes);

    /* get txFecError */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 27, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txFcsError", frame, bytes);

    /* get txMacUnderrun */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 28, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txMacUnderrun", frame, bytes);

    /* get txPktLen < 64B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 29, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txPktLen < 64B", frame, bytes);

    /* get txPktLen == 64B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 30, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txPktLen == 64B", frame, bytes);

    /* get 64B < txPktLen <= 127B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 31, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "64B < txPktLen <= 127B", frame, bytes);

    /* get 127B < txPktLen <= 255B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 32, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "127B < txPktLen <= 255B", frame, bytes);

    /* get 255B < txPktLen <= 511B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 33, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "255B < txPktLen <= 511B", frame, bytes);

    /* get 511B < txPktLen <= 1023B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 34, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "511B < txPktLen <= 1023B", frame, bytes);

    /* get 1023B < txPktLen <= 1518B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 35, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "1023B < txPktLen <= 1518B", frame, bytes);

    /* get 1518B < txPktLen <= 2047B */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 36, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "1518B < txPktLen <= 2047B", frame, bytes);

    /* get 2047B < txPktLen <= MTU1 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 37, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "2047B < txPktLen <= MTU1", frame, bytes);

    /* get MTU1 < txPktLen <= MTU2 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 38, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "MTU1 < txPktLen <= MTU2", frame, bytes);

    /* get txPktLen > MTU2 */
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 39, &frame, &bytes));
    sal_printf("%-30sPkt Num Total:%-20"PRIu64"Byte Num Total:%-20"PRIu64"\n", "txPktLen > MTU2", frame, bytes);

    sal_printf("-------------------------------------------------------------------------------------\n");

    return CTC_E_NONE;
}

int32
sys_at_mac_read_clear(uint8 lchip, uint8 core_id, uint16 mac_group_id, uint8 enable)
{
    uint32 index  = 0;
    uint32 cmd    = 0;
    uint32 value  = 0;
    McMacStats0Cfg_m mac_stats0_cfg;
    McMacStats1Cfg_m mac_stats1_cfg;

    value = enable;
    index = DRV_INS(mac_group_id, 0);

    cmd   = DRV_IOR(McMacStats0Cfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats0_cfg));

    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McMacStats0Cfg_t, mac_group_id, McMacStats0Cfg_cfgClearOnRead0_f, &value, &mac_stats0_cfg);

    cmd   = DRV_IOW(McMacStats0Cfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats0_cfg));

    cmd   = DRV_IOR(McMacStats1Cfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats1_cfg));

    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McMacStats1Cfg_t, mac_group_id, McMacStats1Cfg_cfgClearOnRead1_f, &value, &mac_stats1_cfg);

    cmd   = DRV_IOW(McMacStats1Cfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats1_cfg));

    return CTC_E_NONE;
}

int32
sys_at_mac_clear_stats(uint8 lchip, uint16 lport)
{
    uint8 core_id      = 0;
    uint8 mac_group_id = 0;
    uint8 mac_idx      = 0;
    uint8 port_num     = 0;
    uint8  if_mode     = 0;
    uint16 dport       = 0;
    uint64 bytes       = 0;
    uint64 frame       = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    if ((CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode) || (CTC_CHIP_SERDES_CDG_R8_MODE == if_mode))
    {
        port_num = 8;
    }
    else if (CTC_CHIP_SERDES_CDG_R4_MODE == if_mode)
    {
        port_num = 4;
    }
    else if ((CTC_CHIP_SERDES_CCG_R4_MODE == if_mode) || (CTC_CHIP_SERDES_CCG_R2_MODE == if_mode))
    {
        port_num = 2;
    }
    else
    {
        port_num = 1;
    }

    CTC_ERROR_RETURN(sys_at_mac_read_clear(lchip, core_id, mac_group_id, 1));

    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 0, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 1, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 2, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 3, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 4, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 5, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 6, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 7, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 8, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 9, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 10, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 11, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 12, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 13, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 14, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 15, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 16, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 17, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 18, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 19, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 20, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 21, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 22, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 23, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 24, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 25, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 26, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 27, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 28, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 29, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 30, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 31, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 32, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 33, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 34, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 35, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 36, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 37, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 38, &frame, &bytes));
    CTC_ERROR_RETURN(_sys_at_mac_get_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, 39, &frame, &bytes));

    CTC_ERROR_RETURN(sys_at_mac_read_clear(lchip, core_id, mac_group_id, 0));

#if 0
    for (cnt = 0; cnt < 40; cnt++)
    {
        CTC_ERROR_RETURN(_sys_at_mac_clear_stats(lchip, port_num, core_id, dport, mac_group_id, mac_idx, cnt));
    }
#endif
    return CTC_E_NONE;
}



int32
_sys_at_mac_set_rs_fec_error_inject_cfg_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id, 
                                                     uint8 pcs400_idx, 
                                                     uint8 enable, uint8 insert_mode, uint8 codec_id, 
                                                     uint8 chan_sel, uint32 sym_bmp)
{
    uint8  fld_num = 0;
    reg_field_info_t fld_info[5] = {{0}};

    sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
    fld_num = 0;
    SET_REG_FIELD_INFO(fld_info , fld_num, 0, McPcs400TxFecErrInsert_cfgErrInsertChanSel_f, chan_sel);
    SET_REG_FIELD_INFO(fld_info , fld_num, 0, McPcs400TxFecErrInsert_cfgErrInsertCodecSel_f, codec_id);
    SET_REG_FIELD_INFO(fld_info , fld_num, 0, McPcs400TxFecErrInsert_cfgErrInsertMode_f, insert_mode);
    if(enable)
    {
        SET_REG_FIELD_INFO(fld_info , fld_num, 0, McPcs400TxFecErrInsert_cfgErrInsertSymbBmp_f, sym_bmp);
    }
    SET_REG_FIELD_INFO(fld_info , fld_num, 0, McPcs400TxFecErrInsert_cfgErrInsertEnable_f, enable);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_tx_fec_err_insert(lchip, core_id, 2 * mac_group_id + pcs400_idx, fld_num, fld_info));


    /*if disable, set ErrInsertEnable 0 before BMP 0.*/
    /*BMP address is lower than En, so 2 times IOCTL is necessary to ensure this order.*/
    if (!enable)
    {
        sal_memset(fld_info, 0xff, 5 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info , fld_num, 0, McPcs400TxFecErrInsert_cfgErrInsertSymbBmp_f, 0);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_write_400_tx_fec_err_insert(lchip, core_id, 2 * mac_group_id + pcs400_idx, fld_num, fld_info));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_rs_fec_error_inject_cfg_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id, 
                                                     uint8 pcs400_idx, 
                                                     uint8* p_enable, uint8* p_insert_mode, uint8* p_codec_id, 
                                                     uint8* p_chan_sel, uint32* p_sym_bmp)
{
    uint32 value  = 0;
    reg_field_info_t fld_info[5]        = {{0}};

    SET_REG_SOURCE_FIELD_INFO(fld_info,     0, McPcs400TxFecErrInsert_cfgErrInsertChanSel_f);
    SET_REG_SOURCE_FIELD_INFO(fld_info + 1, 0, McPcs400TxFecErrInsert_cfgErrInsertCodecSel_f);
    SET_REG_SOURCE_FIELD_INFO(fld_info + 2, 0, McPcs400TxFecErrInsert_cfgErrInsertMode_f);
    SET_REG_SOURCE_FIELD_INFO(fld_info + 3, 0, McPcs400TxFecErrInsert_cfgErrInsertSymbBmp_f);
    SET_REG_SOURCE_FIELD_INFO(fld_info + 4, 0, McPcs400TxFecErrInsert_cfgErrInsertEnable_f);
    CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_read_400_tx_fec_err_insert(lchip, core_id, 2 * mac_group_id + pcs400_idx, 5, fld_info));
    value = fld_info[0].value;
    SYS_USW_VALID_PTR_WRITE(p_chan_sel, (uint8)value);
    value = fld_info[1].value;
    SYS_USW_VALID_PTR_WRITE(p_codec_id, (uint8)value);
    value = fld_info[2].value;
    SYS_USW_VALID_PTR_WRITE(p_insert_mode, (uint8)value);
    value = fld_info[3].value;
    SYS_USW_VALID_PTR_WRITE(p_sym_bmp, value);
    value = fld_info[4].value;
    SYS_USW_VALID_PTR_WRITE(p_enable, (uint8)value);

    return CTC_E_NONE;
}

int32
sys_at_mac_set_err_inject(uint8 lchip, uint16 lport, void* p_value)
{
    ctc_port_fec_err_inject_t* p_inj = (ctc_port_fec_err_inject_t*)p_value;
    uint8  encode_id    = 0;
    uint8  inject_mode  = 0;
    uint32 sym_bmp      = 0;
    uint8  enable       = 0;
    uint16 dport        = 0;
    uint8  fec_val      = 0;
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint8  core_id      = 0;
    uint8  pcs400_idx   = 0;
    uint8  codec_id     = 0;
    uint8  chan_sel     = 0;
    uint8  pcs_idx      = 0;
    uint16 if_mode      = 0;
    uint8  prev_en      = 0;
    uint32 prev_sbmp    = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_CONDITION_RETURN(p_inj == NULL, CTC_E_INVALID_PTR);

    encode_id   = p_inj->encode_id;
    inject_mode = p_inj->mode;
    sym_bmp     = p_inj->sym_bmp[0];
    enable      = p_inj->enable;

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_fec_type(lchip, lport, &fec_val));
    SYS_CONDITION_RETURN((SYS_DMPS_FEC_TYPE_NONE == fec_val) || (SYS_DMPS_FEC_TYPE_FC2112 == fec_val), CTC_E_INVALID_CONFIG);

    pcs400_idx   = pcs_idx / 4;

    /*disable injection*/
    CTC_ERROR_RETURN(_sys_at_mac_set_rs_fec_error_inject_cfg_reg(lchip, core_id, mac_group_id, pcs400_idx, 
        0, 0, 0, 0, 0));
    if(CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode)
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_rs_fec_error_inject_cfg_reg(lchip, core_id, mac_group_id, pcs400_idx+1, 
            0, 0, 0, 0, 0));
    }
    if(0 == enable)
    {
        return CTC_E_NONE;
    }

    /*enable injection*/
    switch(if_mode)
    {
        case CTC_CHIP_SERDES_XXVG_MODE:
        case CTC_CHIP_SERDES_LG_MODE:
        case CTC_CHIP_SERDES_LG_R1_MODE:
        case CTC_CHIP_SERDES_XLG_R1_MODE:
        case CTC_CHIP_SERDES_XLG_R2_MODE:
        case CTC_CHIP_SERDES_CG_MODE:
        case CTC_CHIP_SERDES_CG_R2_MODE:
        case CTC_CHIP_SERDES_CG_R1_MODE:
            codec_id = mac_idx % 4 / 2;
            if((SYS_DMPS_FEC_TYPE_RS544INT == fec_val) || (SYS_DMPS_FEC_TYPE_RS272INT == fec_val))
            {
                chan_sel = mac_idx % 2 * 2 + ((0 == encode_id) ? 0 : 1);
            }
            else
            {
                chan_sel = mac_idx % 2 * 2;
            }
            break;
        case CTC_CHIP_SERDES_CCG_R2_MODE:
            codec_id = mac_idx % 4 / 2;
            chan_sel = (0 == encode_id) ? 0 : 2;
            break;
        case CTC_CHIP_SERDES_CCG_R4_MODE:
        case CTC_CHIP_SERDES_CDG_R4_MODE:
        case CTC_CHIP_SERDES_CDG_R8_MODE:
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:
            if((CTC_CHIP_SERDES_DCCCG_R8_MODE == if_mode) && (1 < encode_id))
            {
                pcs400_idx++;
            }
            codec_id = encode_id % 2;
            chan_sel = 0;
            break;
        default:
            break;
    }

    /*if keep enable and bmp changed, do disable before bmp cfg*/
    CTC_ERROR_RETURN(_sys_at_mac_get_rs_fec_error_inject_cfg_reg(lchip, core_id, mac_group_id, pcs400_idx, 
        &prev_en, NULL, NULL, NULL, &prev_sbmp));
    if(prev_en && enable && (prev_sbmp != sym_bmp))
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_rs_fec_error_inject_cfg_reg(lchip, core_id, mac_group_id, pcs400_idx, 
            FALSE, inject_mode, codec_id, chan_sel, sym_bmp));
    }
    /*cfg en & bmp*/
    CTC_ERROR_RETURN(_sys_at_mac_set_rs_fec_error_inject_cfg_reg(lchip, core_id, mac_group_id, pcs400_idx, 
        enable, inject_mode, codec_id, chan_sel, sym_bmp));

    return CTC_E_NONE;
}

int32 
sys_at_mac_get_err_inject(uint8 lchip, uint16 lport, void* p_value)
{
    ctc_port_fec_err_inject_t* p_inj = (ctc_port_fec_err_inject_t*)p_value;
    uint16 dport        = 0;
    uint8  mac_group_id = 0;
    uint8  core_id      = 0;
    uint8  pcs400_idx   = 0;
    uint8  enable       = 0;
    uint8  insert_mode  = 0;
    uint8  codec_id     = 0;
    uint8  chan_sel     = 0;
    uint8  pcs_idx      = 0;
    uint32 sym_bmp      = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_CONDITION_RETURN(p_inj == NULL, CTC_E_INVALID_PTR);

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PCS_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);

    pcs400_idx = pcs_idx / 4;

    CTC_ERROR_RETURN(_sys_at_mac_get_rs_fec_error_inject_cfg_reg(lchip, core_id, mac_group_id, pcs400_idx, 
        &enable, &insert_mode, &codec_id, &chan_sel, &sym_bmp));

    p_inj->sym_bmp[0] = sym_bmp;
    p_inj->sym_bmp_num = 1;
    p_inj->mode = insert_mode;
    p_inj->enable = enable;
    p_inj->encode_id = codec_id;

    return CTC_E_NONE; 
}

int32
_sys_at_cpumac_get_pcs_rst(uint8 lchip, uint8 core_id, uint16 mac_id, uint8 dir, uint8* reset, uint16 dport)
{
    uint8  if_mode = 0;
    uint8  mac_idx = 0;
    uint32 value   = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    if ((CTC_CHIP_SERDES_SGMII_MODE == if_mode) || (CTC_CHIP_SERDES_XFI_MODE == if_mode)
            || (CTC_CHIP_SERDES_XXVG_MODE == if_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == if_mode))
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx,
            ((DMPS_RX == dir) ? SharedPcsSoftRst_softRstPcsRx0_f : SharedPcsSoftRst_softRstPcsTx0_f));

    }
    else if (CTC_CHIP_SERDES_XLG_MODE == if_mode)
    {
        if (DMPS_RX == dir)
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstXlgRx_f);
        }
        else
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstXlgTx_f);
        }
    }
    else if (CTC_CHIP_SERDES_LG_MODE == if_mode)
    {
        if (DMPS_RX == dir)
        {
            if (mac_idx < 2)
            {
                SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstXlgRx_f);
            }
            else
            {
                SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstLgRx_f);
            }
        }
        else
        {
            if (mac_idx < 2)
            {
                SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstXlgTx_f);
            }
            else
            {
                SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstLgTx_f);
            }
        }
    }
    else if (CTC_CHIP_SERDES_CG_MODE == if_mode)
    {
        if (DMPS_RX == dir)
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstCgRx_f);
        }
        else
        {
            SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedPcsSoftRst_softRstCgTx_f);
        }
    }

    CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_shared_pcs_soft_rst(lchip, core_id, 0, 1, &fld_info));
    value = fld_info.value;
    SYS_USW_VALID_PTR_WRITE(reset, value);
    
    return CTC_E_NONE;
}

int32
_sys_at_mac_get_mii_rst(uint8 lchip, uint16 dport, uint8 dir, uint8* reset)
{
    uint8  port_type    = 0;
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint16 mac_id       = 0;
    uint32 fld_id       = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        if(DMPS_RX == dir)
        {
            fld_id = McMacRxSoftReset_cfgMcMacMiiRxSoftReset_f;
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, fld_id);
            sys_usw_dmps_mcmac_reg_read_rx_soft_rst(lchip, core_id, mac_group_id, 1, &fld_info);
        }
        else
        {
            fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
            SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, fld_id);
            sys_usw_dmps_mcmac_reg_read_tx_soft_rst(lchip, core_id, mac_group_id, 1, &fld_info);
        }
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        if(DMPS_RX == dir)
        {
            fld_id = SharedMiiResetCfg_cfgSoftRstRx0_f;
        }
        else
        {
            fld_id = SharedMiiResetCfg_cfgSoftRstTx0_f;
        }
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, fld_id);
        sys_usw_dmps_shared_reg_read_shared_mii_reset_cfg(lchip, core_id, 0, 1, &fld_info);
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% mac %d is not used \n", mac_id);
        return CTC_E_INVALID_PARAM;
    }
    SYS_USW_VALID_PTR_WRITE(reset, fld_info.value);
    return CTC_E_NONE;
}

int32
_sys_at_mac_get_pcs_rst(uint8 lchip, uint16 dport, uint8 dir, uint8* reset)
{
    uint8  port_type    = 0;
    uint8  core_id      = 0;
    uint8  mac_group_id = 0;
    uint8  mac_idx      = 0;
    uint16 mac_id       = 0;
    uint32 fld_id       = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);

    if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        fld_id = (DMPS_RX == dir) ? McPcs800Reset_cfgSoftResetRxChanBmp_f : McPcs800Reset_cfgSoftResetTxChanBmp_f;
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, fld_id);
        CTC_ERROR_RETURN(sys_usw_dmps_mcpcs_reg_read_800_rst(lchip, core_id, mac_group_id, 1, &fld_info));
        SYS_USW_VALID_PTR_WRITE(reset, fld_info.value);
    }
    else if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        CTC_ERROR_RETURN(_sys_at_cpumac_get_pcs_rst(lchip, core_id, mac_id, dir, reset, dport));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% mac %d is not used \n", mac_id);
        return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

int32 sys_at_mac_self_checking_serdes_info(uint8 lchip, uint16 lport)
{
    uint16 idx          = 0;
    uint32 tx_spd       = 0;
    uint32 rx_spd       = 0;
    uint32 tx_rdy       = 0;
    uint32 rx_rdy       = 0;
    uint8  rx_rate      = 0;
    uint8  sd_raw       = 0;
    uint8  sd_f         = 0;
    uint32 pll_sel      = 0;
    uint32 cdr_lock     = 0;
    uint32 dtl_clp      = 0;
    uint8  lpbk_int     = 0;
    uint8  lpbk_loc     = 0;
    uint8  lpbk_ext     = 0;
    uint16 txwidth      = 0;
    uint16 rxwidth      = 0;
    uint32 power_ref    = 0;
    uint32 pu_pll       = 0;
    uint32 pu_tx        = 0;
    uint32 pu_rx        = 0;
    uint32 tx_en        = 0;
    uint32 thrd         = 0;
    uint16 tx_poly      = 0;
    uint16 rx_poly      = 0;
    uint8  pattern_tx   = 0;
    uint32 pattern_rx   = 0;
    uint8  prbs_en_tx   = 0;
    uint32 prbs_en_rx   = 0;
    uint32 rx_train_en  = 0;
    uint32 rx_train_co  = 0;
    uint32 rx_train_fa  = 0;
    uint32 tx_train_en  = 0;
    uint16 tx_train_st  = 0;
    sys_at_serdes_dev_t dev = {0};
    sys_usw_dmps_serdes_id_t psd = {{0}};
    ctc_chip_serdes_loopback_t       loopback    = {0};
    ctc_chip_serdes_ffe_t            ffe         = {0};

    char* tx_train_stat[] = {
        "DISABLE ", 
        "PROGRESS",
        "FAIL    ",    
        "OK      ",      
        "INVALID "
    };
    char* prbs_pat[] = {
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "INVALID ", 
        "PRBS7   ",
        "PRBS9   ",
        "PRBS11  ",
        "PRBS11_0",
        "PRBS11_1",
        "PRBS11_2",
        "PRBS11_3",
        "PRBS15  ",
        "PRBS16  ",
        "PRBS23  ",
        "PRBS31  ",
        "PRBS32  ",
        "PRBS13_0",
        "PRBS13_1",
        "PRBS13_2",
        "PRBS13_3",
    };
    char* txrx_rate[] = {
        "0G       ",
        "1.25G    ",
        "3.125G   ",
        "10.3125G ",
        "11.40625G",
        "12.5G    ",
        "12.96875G",
        "10.9375G ",
        "20.625G  ",
        "25.78125G",
        "28.125G  ",
        "26.5625G ",
        "27.34375G",
        "27.78125G",
        "37.5G    ",
        "39.0625G ",
        "51.5625G ",
        "53.125G  ",
        "56.25G   ",
        "103.125G ",
        "106.25G  ",
        "112.5G   ",
        "42.5G    "
    };

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "---------------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "SerDes Idx BaudRate(G) Type TxPllRdy RxPllRdy SD FcSD PllSel CDRLock DTLclp\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "---------------------------------------------------------------------------\n");
    for(idx = 0; idx < psd.num; idx++)
    {
        _sys_at_get_serdes_dev(lchip, psd.serdes[idx], &dev);
        CTC_ERROR_RETURN(_sys_at_serdes_get_txrx_bit_rate(&dev, &tx_spd, &rx_spd));
        rx_rate = _sys_at_serdes_get_related_serdes_speed((uint8)rx_spd, dev.type);
        CTC_ERROR_RETURN(_sys_at_serdes_get_pll_tx_ready(&dev, &tx_rdy));
        CTC_ERROR_RETURN(_sys_at_serdes_get_pll_rx_ready(&dev, &rx_rdy));
        CTC_ERROR_RETURN(_sys_at_serdes_get_signal_detect(lchip, psd.serdes[idx], &sd_f, &sd_raw));
        CTC_ERROR_RETURN(_sys_at_serdes_get_pll_sel(&dev, &pll_sel));
        CTC_ERROR_RETURN(_sys_at_serdes_get_cdr_lock(lchip, psd.serdes[idx], &cdr_lock));
        CTC_ERROR_RETURN(_sys_at_serdes_get_dtl_clamp(lchip, psd.serdes[idx], &dtl_clp));
        
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6u %-3u %-11s %-4s %-8u %-8u %-2u %-4u %-6u %-7u %-6u\n", psd.serdes[idx], idx, 
            txrx_rate[rx_rate], (SYS_AT_SERDES_56G == dev.type ? "HS":"CS"), tx_rdy, rx_rdy, sd_raw, sd_f, pll_sel, cdr_lock, dtl_clp);
    }
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "---------------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           LpbkMode TxWidth RxWidth Power(ref/pll/tx/rx) TxOutEn SqThrd\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "---------------------------------------------------------------------------\n");
    for(idx = 0; idx < psd.num; idx++)
    {
        _sys_at_get_serdes_dev(lchip, psd.serdes[idx], &dev);

        loopback.serdes_id = psd.serdes[idx];
        loopback.mode = DMPS_SERDES_LPBK_INTERNAL;
        CTC_ERROR_RETURN(_sys_at_serdes_get_loopback(lchip, (void*)(&loopback)));
        lpbk_int = loopback.enable;
        loopback.mode = DMPS_SERDES_LPBK_LOCAL;
        CTC_ERROR_RETURN(_sys_at_serdes_get_loopback(lchip, (void*)(&loopback)));
        lpbk_loc = loopback.enable;
        loopback.mode = DMPS_SERDES_LPBK_EXTERNAL;
        CTC_ERROR_RETURN(_sys_at_serdes_get_loopback(lchip, (void*)(&loopback)));
        lpbk_ext = loopback.enable;
        
        CTC_ERROR_RETURN(_sys_at_serdes_get_data_width(&dev, &txwidth, &rxwidth));
        CTC_ERROR_RETURN(_sys_at_serdes_get_power_ivref(&dev, &power_ref));
        CTC_ERROR_RETURN(_sys_at_serdes_get_lane_power(&dev, &pu_pll, &pu_tx, &pu_rx));
        CTC_ERROR_RETURN(_sys_at_serdes_get_tx_en(&dev, &tx_en));
        CTC_ERROR_RETURN(_sys_at_serdes_get_sq_thrd(&dev, &thrd));

        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           %-8s %-7u %-7u (%-3u %-3u %-3u %-1u)      %-7u %-6u\n", 
            lpbk_int?("TX-RX A"):(lpbk_loc?("TX-RX D"):(lpbk_ext?("RX-TX"):("NONE"))), 
            txwidth, rxwidth, power_ref, pu_pll, pu_tx, pu_rx, tx_en, thrd);
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-----------------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           TxPoly RxPoly TxPRBS(en/patt) RxPRBS(en/patt) FwVer\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-----------------------------------------------------------------------------\n");
    for(idx = 0; idx < psd.num; idx++)
    {
        _sys_at_get_serdes_dev(lchip, psd.serdes[idx], &dev);
        CTC_ERROR_RETURN(_sys_at_serdes_get_polarity(lchip, psd.serdes[idx], 1, &tx_poly));
        CTC_ERROR_RETURN(_sys_at_serdes_get_polarity(lchip, psd.serdes[idx], 0, &rx_poly));
        if(SYS_AT_SERDES_56G == dev.type)
        {
            CTC_ERROR_RETURN(_sys_at_serdes_read_reg_field(&dev, REG_STR(F_AT56G_RX_PAT_SEL), 
                SYS_AT_SERDES_REG_LANE, &pattern_rx));
        }
        else
        {
            CTC_ERROR_RETURN(_sys_at_serdes_read_reg_field(&dev, REG_STR(F_AT112G_RX_PATTERN_SEL), 
                SYS_AT_SERDES_REG_LANE, &pattern_rx));
        }
        CTC_ERROR_RETURN(_sys_at_serdes_get_prbs_rx_enable(&dev, &prbs_en_rx));
        CTC_ERROR_RETURN(_sys_at_serdes_get_prbs_tx(&dev, &prbs_en_tx, &pattern_tx));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           %-6u %-6u (%-1u %-8s)    (%-1u %-8s)      -  \n", tx_poly, rx_poly, 
            prbs_en_tx, prbs_pat[pattern_tx], prbs_en_rx, prbs_pat[pattern_rx]);
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-----------------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           ANLTSM TxTrain(en/stat/cnt) RxTrain(en/co/fa/cnt)\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-----------------------------------------------------------------------------\n");
    for(idx = 0; idx < psd.num; idx++)
    {
        _sys_at_get_serdes_dev(lchip, psd.serdes[idx], &dev);
        CTC_ERROR_RETURN(_sys_at_serdes_get_rx_train_en(&dev, &rx_train_en, &rx_train_co, &rx_train_fa));
        CTC_ERROR_RETURN(_sys_at_serdes_get_training_status(&dev, &tx_train_st));
        CTC_ERROR_RETURN(_sys_at_serdes_get_training_en(&dev, &tx_train_en));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           %-6s (%-3u %-3s %-3s)   (%-3u %-3u %-3u %-3s)\n", "TBD", 
            tx_train_en, tx_train_stat[tx_train_st], "TBD", rx_train_en, rx_train_co, rx_train_fa, "TBD");
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-----------------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           TxEQ\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-----------------------------------------------------------------------------\n");
    for(idx = 0; idx < psd.num; idx++)
    {
        _sys_at_get_serdes_dev(lchip, psd.serdes[idx], &dev);
        ffe.serdes_id = psd.serdes[idx];
        CTC_ERROR_RETURN(_sys_at_serdes_get_txeq_param(lchip, &ffe));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "           (%-3d %-3d %-3d %-3d %-3d %-d)\n", 
            ffe.coefficient[0], ffe.coefficient[1], ffe.coefficient[2], ffe.coefficient[3], ffe.coefficient[4], ffe.coefficient[5]);
    }

    return CTC_E_NONE;
}


int32
sys_at_mac_self_checking(uint8 lchip, uint16 lport)
{
    uint8 serdes_num            = 0;
    uint16 dport                = 0;
    uint16 chan_id              = 0;
    uint16 mac_id               = 0;
    uint16 pcs_id               = 0;
    uint32 fec_val              = 0;
    uint8  serdes_idx           = 0;
    uint32 value                = 0;
    uint8  val_u8               = 0;
    //uint32 temperature          = 0;
    uint8  if_mode              = 0;
    uint8  if_type              = 0;
    uint8  port_type            = 0;
    uint8  speed_mode           = 0;
    uint8  mac_en               = 0;
    uint16 freq                 = 0;
    uint8  invalid_value        = 3;
    ctc_port_fec_cnt_t fec_cnt = {0};
    sys_pcs_status_t   pcs_status = {0};
    uint16  lsd[SYS_MAX_SERDES_NUM_PER_PORT] = {0};
    uint16  psd[SYS_MAX_SERDES_NUM_PER_PORT] = {0};
    uint16  user_serdes = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    char* speed[SYS_PORT_SPEED_MAX] = {
        "1G",   //SYS_PORT_SPEED_1G
        "100M", //SYS_PORT_SPEED_100M
        "10M",  //SYS_PORT_SPEED_10M
        "2.5G", //SYS_PORT_SPEED_2G5
        "10G",  //SYS_PORT_SPEED_10G
        "20G",  //SYS_PORT_SPEED_20G
        "40G",  //SYS_PORT_SPEED_40G
        "100G", //SYS_PORT_SPEED_100G
        "5G",   //SYS_PORT_SPEED_5G
        "25G",  //SYS_PORT_SPEED_25G
        "50G",  //SYS_PORT_SPEED_50G
        "200G", //SYS_PORT_SPEED_200G
        "400G", //SYS_PORT_SPEED_400G
        "800G", //SYS_PORT_SPEED_800G
        "300G"  //SYS_PORT_SPEED_300G
    };
    char* itf[CTC_PORT_IF_MAX_TYPE] = {
        "-"           , //CTC_PORT_IF_NONE
        "SGMII"       , //CTC_PORT_IF_SGMII
        "2500X"       , //CTC_PORT_IF_2500X
        "QSGMII"      , //CTC_PORT_IF_QSGMII
        "USXGMII-S"   , //CTC_PORT_IF_USXGMII_S
        "USXGMII-M2G5", //CTC_PORT_IF_USXGMII_M2G5
        "USXGMII-M5G" , //CTC_PORT_IF_USXGMII_M5G
        "XAUI"        , //CTC_PORT_IF_XAUI
        "D-XAUI"       , //CTC_PORT_IF_DXAUI
        "XFI"         , //CTC_PORT_IF_XFI
        "KR"          , //CTC_PORT_IF_KR
        "CR"          , //CTC_PORT_IF_CR
        "KR2"         , //CTC_PORT_IF_KR2
        "CR2"         , //CTC_PORT_IF_CR2
        "KR4"         , //CTC_PORT_IF_KR4
        "CR4"         , //CTC_PORT_IF_CR4
        "FX"          , //CTC_PORT_IF_FX
        "KR8"         , //CTC_PORT_IF_KR8
        "CR8"         , //CTC_PORT_IF_CR8
        "FLEXE"       , //CTC_PORT_IF_FLEXE
    };
    char* fec[] = {
        "None"  , //SYS_DMPS_FEC_TYPE_NONE
        "RS(528,514)" , //SYS_DMPS_FEC_TYPE_RS528
        "RS(544,514)" , //SYS_DMPS_FEC_TYPE_RS544
        "RS(272,257)" , //SYS_DMPS_FEC_TYPE_RS272
        "Base-R FEC", //SYS_DMPS_FEC_TYPE_FC2112
        "RS(544,514)INT",//SYS_DMPS_FEC_TYPE_RS544INT
        "RS(272,257)INT"//SYS_DMPS_FEC_TYPE_RS272INT
    };

    char* cl37_mode[3] = {
        "1000BASE_X",
        "SGMII_MASTER",
        "SGMII_SLAVER",
    };


#if 0
    char* lt_stat[] = {
        "disable", //SYS_PORT_CL72_DISABLE
        "running", //SYS_PORT_CL72_PROGRESS
        "fail",    //SYS_PORT_CL72_FAIL
        "OK",      //SYS_PORT_CL72_OK
    };
#endif

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Chip Info\n");
#if 0 
    CTC_ERROR_RETURN(sys_at_peri_get_chip_sensor(lchip, CTC_CHIP_SENSOR_TEMP, &temperature));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Chip Temperature", temperature);
#endif 
    CTC_ERROR_RETURN(sys_usw_get_chip_clock(lchip, &freq));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Chip Freq", freq);

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_EN);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PCS_ID,               pcs_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,               mac_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,              chan_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,    if_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,       port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_TYPE,    if_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE, speed_mode);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_EN,          mac_en);
    
    SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, serdes_num);

    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < serdes_num, CTC_E_INVALID_PARAM);
    SYS_CONDITION_RETURN(SYS_PORT_SPEED_MAX <= speed_mode, CTC_E_INVALID_PARAM);
    SYS_CONDITION_RETURN(CTC_PORT_IF_MAX_TYPE <= if_type, CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(_sys_at_mac_get_fec(lchip, dport, &fec_val));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Port Map\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "LPort", lport);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Datapath Channel", chan_id);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "MAC ID", mac_id);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS ID", pcs_id);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: ", "Logical-SerDes");
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_LSD, &serdes_num, lsd));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%02u ", lsd[serdes_idx]);
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: ", "Physical-SerDes");
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_PSD, &serdes_num, psd));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%02u ", psd[serdes_idx]);
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: ", "User-SerDes");
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        sys_at_serdes_psd_to_serdes(lchip, psd[serdes_idx], &user_serdes);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%02u ", user_serdes);
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Port Config\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Speed", speed[speed_mode]);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Interface", itf[if_type]);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "FEC", fec[fec_val]);
    CTC_ERROR_RETURN(_sys_usw_dmps_get_an_en(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Auto-Neg", (0 == value ? "Disable" : "Enable"));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "MAC-EN", 
        (FALSE == mac_en ? "Disable" : "Enable"));
    CTC_ERROR_RETURN(_sys_at_mac_get_mac_pkt_en(lchip, dport, DMPS_RX, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "MAC RX Packet", (0 == value ? "Disable" : "Enable"));
    CTC_ERROR_RETURN(_sys_at_mac_get_mac_pkt_en(lchip, dport, DMPS_TX, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "MAC TX Packet", (0 == value ? "Disable" : "Enable"));
    ///TODO: dmps cannot call port api directly
    /*CTC_ERROR_RETURN(sys_at_port_get_property(lchip, gport, CTC_PORT_PROP_MIN_FRAME_SIZE, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Min frame size", value);
    CTC_ERROR_RETURN(sys_at_port_get_property(lchip, gport, CTC_PORT_PROP_MAX_FRAME_SIZE, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Max frame size", value);*/
    CTC_ERROR_RETURN(sys_at_mac_get_internal_property(lchip, dport, CTC_PORT_PROP_PREAMBLE, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Preamble", value);
    CTC_ERROR_RETURN(_sys_at_mac_get_ipg(lchip, dport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "IPG", value & 0x000000ff);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "SuperG2-EN", (value >> 8));
    CTC_ERROR_RETURN(sys_at_mac_get_internal_property(lchip, dport, CTC_PORT_PROP_PADING_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Padding", value);
    CTC_ERROR_RETURN(sys_at_mac_get_internal_property(lchip, dport, CTC_PORT_PROP_CHK_CRC_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Check-CRC", value);
    CTC_ERROR_RETURN(sys_at_mac_get_internal_property(lchip, dport, CTC_PORT_PROP_STRIP_CRC_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Strip-CRC", value);
    CTC_ERROR_RETURN(sys_at_mac_get_internal_property(lchip, dport, CTC_PORT_PROP_APPEND_CRC_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Append-CRC", value);
    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        (void)sys_at_mac_get_internal_property(lchip, dport, CTC_PORT_PROP_APPEND_TOD_EN, &value);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Append-TOD", value);
    }
    else if(SYS_DMPS_NETWORK_PORT == port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Append-TOD", "-");
    }
    if(SYS_MAC_IS_MODE_SUPPORT_CL37(if_mode))       
    {
        if(if_mode == CTC_CHIP_SERDES_SGMII_MODE || if_mode == CTC_CHIP_SERDES_2DOT5G_MODE)
        {
            CTC_ERROR_RETURN(_sys_at_mac_get_parallel_detect_en(lchip, dport, &value));
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Parallel detect enable", value ? "Enable" : "Disable");
        }
        CTC_ERROR_RETURN(_sys_at_mac_get_cl37_auto_neg(lchip, dport, CTC_PORT_PROP_AUTO_NEG_MODE, &value));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Autoneg Mode", cl37_mode[value]);
    }
    else if(SYS_MAC_IS_MODE_SUPPORT_CL73(if_mode))  
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: \n", "configured cl73 local ability");
        CTC_ERROR_RETURN(sys_usw_dmps_get_mac_property_dispatch(lchip, lport, CTC_PORT_PROP_CL73_ABILITY, &value));
        _sys_usw_mac_show_cl73_ability(value);

        CTC_ERROR_RETURN(sys_usw_dmps_get_mac_property_dispatch(lchip, lport, CTC_PORT_PROP_AUTO_NEG_FEC, &value));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: ", "cl73 fec");
        if(value == 0)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%s ", "NONE");
        }
        if (value & (1 << CTC_PORT_FEC_TYPE_RS))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%s ", "RS-FEC");
        }
        if (value & (1 << CTC_PORT_FEC_TYPE_BASER))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%s ", "BASE-R FEC");
        }
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"\n");
        CTC_ERROR_RETURN(sys_usw_dmps_get_mac_property_dispatch(lchip, lport, CTC_PORT_PROP_AUTO_NEG_MODE, &value));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Autoneg Mode", (0 == value ? "Default mode" : "OverClock Mode"));
    }
    CTC_ERROR_RETURN(_sys_at_mac_get_link_intr(lchip, dport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "pcs link intr", value ? "Enable" : "Disable");
    CTC_ERROR_RETURN(_sys_at_mac_get_unidir_en(lchip, dport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "undir enable", value ? "Enable" : "Disable"); 
    CTC_ERROR_RETURN(_sys_at_mac_get_link_filter(lchip, dport, SYS_MAC_LINK_FILTER, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %ums\n", "Link filter", value);
    CTC_ERROR_RETURN(_sys_at_mac_get_link_filter(lchip, dport, SYS_MAC_FAULT_FILTER, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %ums\n", "Fault filter", value);
    value = 0;
    CTC_ERROR_RETURN(_sys_at_mac_get_tx_force_fault(lchip, dport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "TX force fault", 
        CTC_FLAG_ISSET(value, CTC_PORT_FAULT_FORCE) ? "enable" : "disable");
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_rst(lchip, dport, DMPS_RX, &val_u8));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS RX reset", val_u8);
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_rst(lchip, dport, DMPS_TX, &val_u8));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS TX reset", val_u8);
    CTC_ERROR_RETURN(_sys_at_mac_get_mii_rst(lchip, dport, DMPS_RX, &val_u8));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "MII RX reset", val_u8);
    CTC_ERROR_RETURN(_sys_at_mac_get_mii_rst(lchip, dport, DMPS_TX, &val_u8));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "MII TX reset", val_u8);
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "MAC Status\n");
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode_by_dport(lchip, dport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Link mode", (value == LINK_MODE_PCS_PMA ? "PCS-PMA" : "STANDALONE"));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_fsm(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Link FSM", value);    
    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, 0, SYS_MAC_MII_LINK_FM, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Link status", (0 == value ? "down" : "up"));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, 0, SYS_MAC_MII_LINK_RAW, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Link status raw", (0 == value ? "down" : "up"));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_fault(lchip, dport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "RX fault status", value);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Local fault", CTC_FLAG_ISSET(value, CTC_PORT_FAULT_LOCAL));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Remote fault", CTC_FLAG_ISSET(value, CTC_PORT_FAULT_REMOTE));
#if 0 
    CTC_ERROR_RETURN(_sys_tmm_mac_get_voq_status(lchip, gport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "VOQ cell status", value);
#endif
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "PCS/PMD Status\n");
    CTC_ERROR_RETURN(sys_at_mac_pcs_status_check(lchip, dport, &pcs_status));

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "pcs_sync", pcs_status.pcs_sync);

    if(invalid_value == pcs_status.hi_ber)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "hi_ber", "-");
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "hi_ber", pcs_status.hi_ber);
    }

    if(SYS_AT_USELESS_ID8 == pcs_status.bad_ber_cnt)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "bad_ber_cnt", "-");
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "bad_ber_cnt", pcs_status.bad_ber_cnt);
    }

    if(SYS_AT_USELESS_ID8 == pcs_status.err_blk_cnt)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Error block Cnt", "-");
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Error block Cnt", pcs_status.err_blk_cnt);
    }

    if(invalid_value == pcs_status.rx_cwm_lock)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RxCwmLock", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "RxCwmLock", pcs_status.rx_cwm_lock); 
    }  
    if(invalid_value == pcs_status.rx_block_lock)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RxBlockLock", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RxBlockLock", (pcs_status.rx_block_lock != 0) ? "ok" : "fail"); 
    }
    if(invalid_value == pcs_status.rx_am_lock)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RxAmLock", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RxAmLock", (pcs_status.rx_am_lock != 0) ? "ok" : "fail"); 
    }
    if(invalid_value == pcs_status.fec_am_lock)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "FecAmLock", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "FecAmLock", (pcs_status.fec_am_lock != 0) ? "ok" : "fail"); 
    }
    if(invalid_value == pcs_status.xgfec_lock)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "XgFecLock", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "XgFecLock", (pcs_status.xgfec_lock != 0) ? "ok" : "fail"); 
    }
    if(invalid_value == pcs_status.rsfec_lock)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RsFecLock", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "RsFecLock", (pcs_status.rsfec_lock != 0) ? "ok" : "fail"); 
    }
    if(SYS_AT_USELESS_ID8 == pcs_status.bip_err_cnt)
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "BipErrCnt", "-");
    }
    else
    {
          SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "BipErrCnt", pcs_status.bip_err_cnt); 
    } 

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "CodeErrCnt", pcs_status.code_err_cnt); 

    if (CTC_E_NONE == _sys_at_mac_get_fec_cnt(lchip, dport, (void*)(&fec_cnt)))
    {
        _sys_at_mac_self_check_fec_cnt_print(&fec_cnt, fec_val);
    }

    (void)sys_at_mac_self_checking_serdes_info(lchip, lport);

    return CTC_E_NONE;

}

int32
sys_at_mac_get_sfd_en(uint8 lchip, uint16 lport, uint32 *enable)
{
    uint8  port_type = 0;
    uint8  mac_grp = 0;
    uint8  mac_idx = 0;
    uint8  core_id = 0;
    uint16 dport   = 0;
    uint32 value   = 0;
    reg_field_info_t fld_info        = {0};
    sys_dmps_db_upt_info_t port_info = {0};

    dport = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    if (!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_grp);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, 0, SharedMii0Cfg_cfgMiiSfdValue0_f);
        CTC_ERROR_RETURN(sys_usw_dmps_shared_reg_read_sharedmii0cfg(lchip, core_id, 0, mac_idx, 1, &fld_info));
        value = fld_info.value;
    }
    else
    {
        SET_REG_SOURCE_FIELD_INFO(&fld_info, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiSfdValue_f);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_read_mii_rx_cfg(lchip, core_id, mac_grp, 1, &fld_info));
        value = fld_info.value;
    }

    *enable = (0x5d == value) ? 1 : 0;

    return CTC_E_NONE;
}

int32
sys_at_mac_set_sfd_en(uint8 lchip, uint16 lport, uint32 enable)
{
    uint8  port_type = 0;
    uint8  mac_grp = 0;
    uint8  mac_idx = 0;
    uint8  core_id = 0;
    uint8  fld_num = 0;
    uint16 dport   = 0;
    uint32 cmd     = 0;
    uint32 index   = 0;
    uint32 tbl_id  = 0;
    uint32 value   = (enable ? 0x5d : 0xd5);
    uint32 step    = 0;
    reg_field_info_t fld_info[2]     = {{0}};
    sys_dmps_db_upt_info_t port_info = {0};
    SharedMii0Cfg_m mii_per_cfg;

    dport = sys_usw_dmps_db_get_dport_by_lport(lchip, lport);
    if (!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_GROUP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_MAC_IDX);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,    port_type);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_grp);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);

    if(SYS_USW_IS_CPUMAC_PORT(port_type))
    {
        step   = SharedMii1Cfg_t - SharedMii0Cfg_t;
        tbl_id = SharedMii0Cfg_t + mac_idx * step;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mii_per_cfg));

        DRV_IOW_FIELD(lchip, tbl_id, 0, SharedMii0Cfg_cfgMiiSfdValue0_f, &value, &mii_per_cfg);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mii_per_cfg));
    }
    else
    {
        sal_memset(fld_info, 0xff, 1 * sizeof(reg_field_info_t));
        fld_num = 0;
        SET_REG_FIELD_INFO(fld_info, fld_num, mac_idx, McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiSfdValue_f, value);
        CTC_ERROR_RETURN(sys_usw_dmps_mcmac_reg_write_mii_rx_cfg(lchip, core_id, mac_grp, fld_num, fld_info));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_prbs_rx_en(uint8 lchip, void* p_psd, uint32* p_prbs_en)
{
    uint8  idx     = 0;
    uint32 en_lane = 0;
    uint32 en      = 0;
    sys_at_serdes_dev_t dev = {0};
    sys_usw_dmps_serdes_id_t* psd = (sys_usw_dmps_serdes_id_t*)p_psd;

    SYS_CONDITION_RETURN(NULL == psd, CTC_E_INVALID_PTR);

    dev.lchip = lchip;
    dev.type = _sys_at_datapath_get_serdes_type(psd->serdes[0]);
    for(idx = 0; idx < psd->num; idx++)
    {
        dev.serdes_id = psd->serdes[idx];
        CTC_ERROR_RETURN(_sys_at_serdes_get_prbs_rx_enable(&dev, &en_lane));
        if(en_lane)
        {
            en = 1;
            break;
        }
    }
    SYS_USW_VALID_PTR_WRITE(p_prbs_en, en);

    return CTC_E_NONE;
}

int32
_sys_at_mac_get_loopback_mode(uint8 lchip, void* p_psd, uint32* p_lpbk_mode)
{
    uint8  idx       = 0;
    uint32 mode_lane = DMPS_SERDES_LPBK_NONE;
    uint32 mode      = DMPS_SERDES_LPBK_NONE;
    ctc_chip_serdes_loopback_t lpbk = {0};
    sys_usw_dmps_serdes_id_t* psd = (sys_usw_dmps_serdes_id_t*)p_psd;

    SYS_CONDITION_RETURN(NULL == psd, CTC_E_INVALID_PTR);

    for(mode_lane = DMPS_SERDES_LPBK_INTERNAL; mode_lane < DMPS_SERDES_LPBK_NONE; mode_lane++)
    {
        lpbk.mode = mode_lane;
        for(idx = 0; idx < psd->num; idx++)
        {
            lpbk.serdes_id = psd->serdes[idx];
            CTC_ERROR_RETURN(_sys_at_serdes_get_loopback(lchip, (void*)(&lpbk)));
            if(lpbk.enable)
            {
                mode = mode_lane;
                break;
            }
        }
        SYS_CONDITION_BREAK(mode != DMPS_SERDES_LPBK_NONE);
    }
    SYS_USW_VALID_PTR_WRITE(p_lpbk_mode, mode);
    return CTC_E_NONE;
}


int32
_sys_at_mac_link_fsm_nonready_proc(uint8 lchip, uint16 lport)
{
    uint32 link_mode = LINK_MODE_PCS_PMA;
    uint32 an_en     = 0;
    uint32 mac_en    = 0;
    uint16 dport     = 0;
    uint8  sig_vld   = 0;
    uint32 pcs_up    = 0;
    uint32 prbs_en   = 0;
    uint32 lpbk      = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_NONREADY: (lport %u, link_mode %u, an_en %u) go to PMA_RX_COVER\n", 
            lport, link_mode, an_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_0, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    /*1. judge if mac disable*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_en(lchip, lport, &mac_en));
    if(!mac_en)
    {
        return CTC_E_NONE;
    }

    /*1.1 judge if prbs test enable, stay in current STATE*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));
    CTC_ERROR_RETURN(_sys_at_mac_get_prbs_rx_en(lchip, (void*)(&psd), &prbs_en));
    if(prbs_en)
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_1, (uint16)prbs_en);
        return CTC_E_NONE;
    }

    /*1.2 judge if loopback enable, jump to STATE PCS_SYNC*/
    CTC_ERROR_RETURN(_sys_at_mac_get_loopback_mode(lchip, (void*)(&psd), &lpbk));
    if(DMPS_SERDES_LPBK_LOCAL == lpbk)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_NONREADY: (lport %u, lpbk %u) go to PMA_RX_PCS_SYNC1\n", 
            lport, lpbk);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_2, (uint16)lpbk);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_PCS_SYNC1));
        return CTC_E_NONE;
    }

    /*2. judge signal valid*/
    CTC_ERROR_RETURN(_sys_at_mac_get_signal_valid(lchip, (void*)(&psd), &sig_vld));
    if(RX_NO_SIGNAL == sig_vld)
    {
        /*optional PMA recovery*/
        return CTC_E_NONE;
    }

    /*3. judge pcs_up to start pre train, or directly jump to post train*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_link_status(lchip, dport, &pcs_up));
    if(pcs_up)
    {
        /*enable rx train*/
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_NONREADY: (lport %u, pcs_up %u) enable POST_TRAIN then go to PMA_RX_POST_TRAIN1\n", 
            lport, pcs_up);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_3, (uint16)pcs_up);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), TRUE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_POST_TRAIN1));
    }
    else
    {
        /*enable init train*/
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_NONREADY: (lport %u, pcs_up %u) enable PRE_TRAIN then go to PMA_RX_PRE_TRAIN1\n", 
            lport, pcs_up);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_4, (uint16)pcs_up);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), TRUE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_PRE_TRAIN1));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_pretrain_proc(uint8 lchip, uint16 lport, uint32 fsm)
{
    uint32 link_mode  = LINK_MODE_PCS_PMA;
    uint32 an_en      = 0;
    uint32 mac_en     = 0;
    uint8  train_stat = 0;
    uint32 prbs_en    = 0;
    uint32 lpbk       = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, link_mode %u, an_en %u, fsm %u) go to PMA_RX_COVER\n", 
            lport, link_mode, an_en, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_5, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    /*1. judge if mac disable*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_en(lchip, lport, &mac_en));
    if(!mac_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, mac_en %u) disable PRE_TRAIN then go to PMA_RX_NONREADY\n", 
            lport, mac_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_6, (uint16)mac_en);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    /*1.1 judge if prbs test enable, stay in current STATE*/
    CTC_ERROR_RETURN(_sys_at_mac_get_prbs_rx_en(lchip, (void*)(&psd), &prbs_en));
    if(prbs_en)
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_1, (uint16)prbs_en);
        return CTC_E_NONE;
    }

    /*1.2 judge if loopback enable, disable PRE_TRAIN and jump to STATE PCS_SYNC*/
    CTC_ERROR_RETURN(_sys_at_mac_get_loopback_mode(lchip, (void*)(&psd), &lpbk));
    if(DMPS_SERDES_LPBK_LOCAL == lpbk)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, lpbk %u, fsm %u) disable PRE_TRAIN then go to PMA_RX_PCS_SYNC\n", 
            lport, lpbk, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_7, (uint16)lpbk);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_PCS_SYNC1));
        return CTC_E_NONE;
    }

    /*2. judge pre train status: RUN - wait or timeout; FAIL/STOP - jump to NONREADY; SUCCESS - jump to INIT_DONE*/
    CTC_ERROR_RETURN(_sys_at_mac_get_port_rx_train_stat(lchip, (void*)(&psd), &train_stat));
    if(RX_TRAIN_RUN == train_stat) /*still running*/
    {
        if(PMA_RX_PRE_TRAIN3 <= fsm) /*timeout*/
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, train_stat %u, fsm %u) disable PRE_TRAIN then go to PMA_RX_NONREADY\n", 
                lport, train_stat, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_8, (uint16)train_stat);
            CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
            /*optional PMA recovery*/
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        }
        else /*running*/
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, train_stat %u, fsm %u) go to PMA_RX_PRE_TRAIN(n+1)\n", 
                lport, train_stat, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_9, (uint16)fsm);
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, fsm+1));
        }
    }
    else if((RX_TRAIN_FAIL == train_stat) || (RX_TRAIN_STOP == train_stat)) /*fail*/
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, train_stat %u, fsm %u) disable PRE_TRAIN then go to PMA_RX_NONREADY\n", 
            lport, train_stat, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_10, 
            ((uint16)((fsm << 8) & 0xff00) | (uint16)(train_stat & 0x00ff)));
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
    }
    else /*success*/
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PRE_TRAIN: (lport %u, train_stat %u, fsm %u) disable PRE_TRAIN then go to PMA_RX_PCS_SYNC\n", 
            lport, train_stat, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_11, (uint16)train_stat);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_PCS_SYNC1));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_pcssync_proc(uint8 lchip, uint16 lport, uint32 fsm)
{
    uint32 link_mode = LINK_MODE_PCS_PMA;
    uint32 an_en     = 0;
    uint32 mac_en    = 0;
    uint16 dport     = 0;
    uint8  sig_vld   = 0;
    uint32 pcs_up    = 0;
    uint32 prbs_en   = 0;
    uint32 lpbk      = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, link_mode %u, an_en %u, fsm %u) go to PMA_RX_COVER\n", 
            lport, link_mode, an_en, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_12, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    /*1. judge if mac disable*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_en(lchip, lport, &mac_en));
    if(!mac_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, mac_en %u) go to PMA_RX_NONREADY\n", 
            lport, mac_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_13, (uint16)mac_en);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    /*1.1 judge if prbs test enable, stay in current STATE*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));
    CTC_ERROR_RETURN(_sys_at_mac_get_prbs_rx_en(lchip, (void*)(&psd), &prbs_en));
    if(prbs_en)
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_1, (uint16)prbs_en);
        return CTC_E_NONE;
    }

    /*1.2 judge if loopback enable, then if pcs_up jump to STATE POST_TRAIN, else wait 1 more period*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_link_status(lchip, dport, &pcs_up));
    CTC_ERROR_RETURN(_sys_at_mac_get_loopback_mode(lchip, (void*)(&psd), &lpbk));
    if(DMPS_SERDES_LPBK_LOCAL == lpbk)
    {
        if(pcs_up)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, pcs_up %u, lpbk %u) go to PMA_RX_POST_TRAIN\n", 
                lport, pcs_up, lpbk);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_14, (uint16)lpbk);
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_POST_TRAIN1));
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, pcs_up %u, lpbk %u) waiting pcs up\n", 
                lport, pcs_up, lpbk);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_15, (uint16)lpbk);
        }
        return CTC_E_NONE;
    }

    /*2. judge signal valid*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));
    CTC_ERROR_RETURN(_sys_at_mac_get_signal_valid(lchip, (void*)(&psd), &sig_vld));
    if(RX_VALID_SIGNAL != sig_vld)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, sig_vld %u) go to PMA_RX_NONREADY\n", 
            lport, sig_vld);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_16, (uint16)sig_vld);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        /*optional PMA recovery*/
        return CTC_E_NONE;
    }

    /*3. judge pcs_up to start post train, or wait 1 more period, or restart pre-train*/
    if(pcs_up)
    {
        /*enable rx train*/
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, pcs_up %u, fsm %u) enable POST_TRAIN then go to PMA_RX_POST_TRAIN\n", 
            lport, pcs_up, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_17, (uint16)fsm);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), TRUE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_POST_TRAIN1));
    }
    else
    {
        if(PMA_RX_PCS_SYNC1 == fsm) /*wait 1 more period*/
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, pcs_up %u, fsm %u) go to PCS_SYNC(n+1)\n", 
                lport, pcs_up, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_18, (uint16)fsm);
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, fsm+1));
        }
        else /*restart pre-train*/
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_PCS_SYNC: (lport %u, pcs_up %u, fsm %u) enable PRE_TRAIN then go to PMA_RX_PRE_TRAIN\n", 
                lport, pcs_up, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_41, (uint16)pcs_up);
            CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), TRUE));
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_PRE_TRAIN1));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_cl37_retrigger(uint8 lchip, uint16 lport, uint16 psd)
{
    uint32 cl37_en = 0;
    sys_at_serdes_dev_t dev = {0};
    int32 ret = sys_at_mac_get_cl37_en(lchip, lport, &cl37_en);

    SYS_CONDITION_RETURN((CTC_E_NONE != ret) || (0 == cl37_en), CTC_E_NONE);

    _sys_at_get_serdes_dev(lchip, psd, &dev);
    CTC_ERROR_RETURN(_sys_at_serdes_set_tx_en(&dev, 0));
    sal_udelay(1000);
    CTC_ERROR_RETURN(_sys_at_serdes_set_tx_en(&dev, 1));
    
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_42, psd);

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_posttrain_proc(uint8 lchip, uint16 lport, uint32 fsm)
{
    uint32 link_mode  = LINK_MODE_PCS_PMA;
    uint32 an_en      = 0;
    uint32 mac_en     = 0;
    uint8  train_stat = 0;
    uint8  sig_vld    = 0;
    uint16 dport      = 0;
    uint32 prbs_en    = 0;
    uint32 lpbk       = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));
    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, 
            "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, link_mode %u, an_en %u, fsm %u) disable POST_TRAIN then go to PMA_RX_COVER\n", lport, link_mode, an_en, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_19, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    /*1. judge if mac disable*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_en(lchip, lport, &mac_en));
    if(!mac_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, mac_en %u) disable POST_TRAIN then go to PMA_RX_NONREADY\n", 
            lport, mac_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_20, (uint16)mac_en);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    /*1.1 judge if prbs test enable, stay in current STATE*/
    CTC_ERROR_RETURN(_sys_at_mac_get_prbs_rx_en(lchip, (void*)(&psd), &prbs_en));
    if(prbs_en)
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_1, (uint16)prbs_en);
        return CTC_E_NONE;
    }

    /*1.2 judge if loopback enable, disable POST_TRAIN and jump to STATE RX_TRAIN_DONE*/
    CTC_ERROR_RETURN(_sys_at_mac_get_loopback_mode(lchip, (void*)(&psd), &lpbk));
    if(DMPS_SERDES_LPBK_LOCAL == lpbk)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, lpbk %u, fsm %u) disable POST_TRAIN then go to RX_TRAIN_DONE\n", 
            lport, lpbk, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_21, (uint16)lpbk);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        /*release all reset*/
        CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, RST_PCS_0_MAC_0));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_TRAIN_DONE));
        return CTC_E_NONE;
    }

    /*2. judge post train status: RUN - wait or timeout; FAIL/STOP - jump to NONREADY; SUCCESS - jump to READY*/
    CTC_ERROR_RETURN(_sys_at_mac_get_port_rx_train_stat(lchip, (void*)(&psd), &train_stat));
    if(RX_TRAIN_RUN == train_stat) /*still running*/
    {
        if(PMA_RX_POST_TRAIN3 <= fsm) /*timeout*/
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, train_stat %u, fsm %u) disable POST_TRAIN then go to PMA_RX_NONREADY\n", 
                lport, train_stat, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_22, (uint16)fsm);
            CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
            /*optional PMA recovery*/
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        }
        else /*running*/
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, train_stat %u, fsm %u) go to PMA_RX_POST_TRAIN(n+1)\n", 
                lport, train_stat, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_23, (uint16)fsm);
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, fsm+1));
        }
    }
    else if((RX_TRAIN_FAIL == train_stat) || (RX_TRAIN_STOP == train_stat)) /*fail*/
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, train_stat %u, fsm %u) disable POST_TRAIN then go to PMA_RX_NONREADY\n", 
            lport, train_stat, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_24, (uint16)fsm);
        CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
    }
    else /*success*/
    {
        CTC_ERROR_RETURN(_sys_at_mac_get_signal_valid(lchip, (void*)(&psd), &sig_vld));
        if(RX_VALID_SIGNAL != sig_vld)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_TRAIN_DONE: (lport %u, sig_vld %u) set RX rst to default then go to PMA_RX_NONREADY\n", 
                lport, sig_vld);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_28, (uint16)sig_vld);
            CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, RST_PCS_0_MAC_1));
            /*optional PMA recovery*/
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
            return CTC_E_NONE;
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_POST_TRAIN: (lport %u, train_stat %u, fsm %u) disable POST_TRAIN, release all RX reset, then go to PMA_RX_TRAIN_DONE\n", 
                lport, train_stat, fsm);
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_25, (uint16)fsm);
            CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
            /*release all reset*/
            CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, RST_PCS_0_MAC_0));
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_cl37_retrigger(lchip, lport, psd.serdes[0]));
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_TRAIN_DONE));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_traindone_proc(uint8 lchip, uint16 lport)
{
    uint32 link_mode = LINK_MODE_PCS_PMA;
    uint32 an_en     = 0;
    uint32 mac_en    = 0;
    uint16 dport     = 0;
    uint8  sig_vld   = 0;
    uint32 pcs_up    = 0;
    uint32 prbs_en   = 0;
    uint32 lpbk      = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_TRAIN_DONE: (lport %u, link_mode %u, an_en %u) go to PMA_RX_COVER\n", 
            lport, link_mode, an_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_26, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    /*1. judge if mac disable*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_en(lchip, lport, &mac_en));
    if(!mac_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_TRAIN_DONE: (lport %u, mac_en %u) go to PMA_RX_NONREADY\n", 
            lport, mac_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_27, (uint16)mac_en);
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    /*1.1 judge if prbs test enable, stay in current STATE*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));
    CTC_ERROR_RETURN(_sys_at_mac_get_prbs_rx_en(lchip, (void*)(&psd), &prbs_en));
    if(prbs_en)
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_1, (uint16)prbs_en);
        return CTC_E_NONE;
    }
    /*1.2 judge if loopback enable, jump to RX_READY*/
    CTC_ERROR_RETURN(_sys_at_mac_get_loopback_mode(lchip, (void*)(&psd), &lpbk));
    if(DMPS_SERDES_LPBK_LOCAL == lpbk)
    {
        CTC_ERROR_RETURN(_sys_at_mac_get_pcs_link_status(lchip, dport, &pcs_up));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_TRAIN_DONE: (lport %u, pcs_up %u) lpbk en go to PMA_RX_READY\n", 
            lport, pcs_up);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_40, (uint16)pcs_up);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_READY));
        return CTC_E_NONE;
    }

    /*2. judge signal valid */
    CTC_ERROR_RETURN(_sys_at_mac_get_signal_valid(lchip, (void*)(&psd), &sig_vld));
    if(RX_VALID_SIGNAL != sig_vld)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_TRAIN_DONE: (lport %u, sig_vld %u) set RX rst to default then go to PMA_RX_NONREADY\n", 
            lport, sig_vld);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_28, (uint16)sig_vld);
        CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, RST_PCS_0_MAC_1));
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    /*3. jump to RX_READY FSM, no matter pcs up or down*/
    CTC_ERROR_RETURN(_sys_at_mac_get_pcs_link_status(lchip, dport, &pcs_up));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_TRAIN_DONE: (lport %u, pcs_up %u) go to PMA_RX_READY\n", 
        lport, pcs_up);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_29, (uint16)pcs_up);
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_READY));

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_rxready_proc(uint8 lchip, uint16 lport)
{
    uint32 link_mode  = LINK_MODE_PCS_PMA;
    uint32 an_en      = 0;
    uint32 mac_en     = 0;
    uint16 dport      = 0;
    uint32 mii_up     = 0;
    uint32 prbs_en    = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_READY: (lport %u, link_mode %u, an_en %u) go to PMA_RX_COVER\n", 
            lport, link_mode, an_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_30, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    /*1. judge if mac disable*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_en(lchip, lport, &mac_en));
    if(!mac_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_READY: (lport %u, mac_en %u) go to PMA_RX_NONREADY\n", 
            lport, mac_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_31, (uint16)mac_en);
        /*optional PMA recovery*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    /*1.1 judge if prbs test enable, stay in current STATE*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));
    CTC_ERROR_RETURN(_sys_at_mac_get_prbs_rx_en(lchip, (void*)(&psd), &prbs_en));
    if(prbs_en)
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_1, (uint16)prbs_en);
        return CTC_E_NONE;
    }

    /*2. judge MII status: up - link adjust; down - set mac-pcs as before, then go to NONREADY*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, FALSE, SYS_MAC_MII_LINK_RAW, &mii_up));
    if(!mii_up)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_READY: (lport %u, mii_up %u) set RX rst to default then go to PMA_RX_NONREADY\n", 
            lport, mii_up);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_32, (uint16)mii_up);
        CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, RST_PCS_0_MAC_1));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
    }
    else
    {
        CTC_ERROR_RETURN(sys_at_mcu_send_link_adjust_intr(lchip, dport));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_rxcover_proc(uint8 lchip, uint16 lport)
{
    uint16 dport      = 0;
    uint32 mii_up     = 0;
    uint32 link_mode  = LINK_MODE_PCS_PMA;
    uint32 an_en      = 0;

    /*0. judge standalone mode*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE != link_mode) && (1 != an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] PMA_RX_COVER: lport %u, link_mode %u, an_en %u\n", lport, link_mode, an_en);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_33, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));
    CTC_ERROR_RETURN(_sys_at_mac_get_link_up(lchip, dport, FALSE, SYS_MAC_MII_LINK_RAW, &mii_up));

    if (mii_up)
    {
        CTC_ERROR_RETURN(sys_at_mcu_send_link_adjust_intr(lchip, dport));
    }

    return CTC_E_NONE;
}

int32
_sys_at_mac_link_fsm_exception_proc(uint8 lchip, uint16 lport, uint32 fsm)
{
    uint32 link_mode  = LINK_MODE_PCS_PMA;
    uint32 an_en      = 0;
    uint16 dport      = 0;
    sys_usw_dmps_serdes_id_t psd = {{0}};

    /*0. judge standalone mode and jump to PMA_RX_COVER*/
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_link_mode(lchip, lport, &link_mode));
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_an_en(lchip, lport, &an_en));
    if((LINK_MODE_STDALONE == link_mode) || (1 == an_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] exception: (lport %u, link_mode %u, an_en %u, fsm %u) go to PMA_RX_COVER\n", 
            lport, link_mode, an_en, fsm);
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_34, 
            ((uint16)((link_mode << 8) & 0xff00) | (uint16)(an_en & 0x00ff)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_COVER));
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_psd_by_lport(lchip, lport, psd.serdes, &(psd.num)));

    CTC_ERROR_RETURN(_sys_at_mac_set_port_rx_train_en(lchip, (void*)(&psd), FALSE));
    CTC_ERROR_RETURN(sys_usw_dmps_db_lport_2_dport(lchip, lport, &dport));
    CTC_ERROR_RETURN(_sys_at_mac_set_rx_rst_condition(lchip, dport, RST_PCS_0_MAC_1));
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_link_fsm(lchip, lport, PMA_RX_NONREADY));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[DAEMON] exception: (lport %u, fsm %u) disable RX TRAIN then go to PMA_RX_NONREADY\n", 
        lport, fsm);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LINK_FSM_35, 1);

    return CTC_E_NONE;
}

int32
sys_at_mac_daemon_thread(uint8 lchip, uint16 lport)
{
    uint32 fsm = PMA_RX_NONREADY;

    SYS_CONDITION_RETURN(CTC_E_NONE != sys_usw_dmps_db_get_link_fsm(lchip, lport, &fsm), CTC_E_NONE);
    /*SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "\n_sys_at_mac_daemon_thread: lport %u, fsm %u\n", lport, fsm);*/
    switch(fsm)
    {
        case PMA_RX_NONREADY   :
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_nonready_proc(lchip, lport));
            break;
        case PMA_RX_PRE_TRAIN1 :
        case PMA_RX_PRE_TRAIN2 :
        case PMA_RX_PRE_TRAIN3 :
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_pretrain_proc(lchip, lport, fsm));
            break;
        case PMA_RX_PCS_SYNC1  :
        case PMA_RX_PCS_SYNC2  :
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_pcssync_proc(lchip, lport, fsm));
            break;
        case PMA_RX_POST_TRAIN1:
        case PMA_RX_POST_TRAIN2:
        case PMA_RX_POST_TRAIN3:
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_posttrain_proc(lchip, lport, fsm));
            break;
        case PMA_RX_TRAIN_DONE :
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_traindone_proc(lchip, lport));
            break;
        case PMA_RX_READY      :
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_rxready_proc(lchip, lport));
            break;
        case PMA_RX_COVER      :
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_rxcover_proc(lchip, lport));
            break;
        default:
            CTC_ERROR_RETURN(_sys_at_mac_link_fsm_exception_proc(lchip, lport, fsm));
            break;    
    }

    return CTC_E_NONE;
}


